tree 071c69c58f9fcc58ac3039004e0f41d9cd8ce6e2
parent 8f6330a807f2642dc2a3cdf33347aa28a4c00a87
parent 301876597112218c1e465ecc2b2fef6b27d5c27b
author Peter Maydell <peter.maydell@linaro.org> 1709898421 +0000
committer Peter Maydell <peter.maydell@linaro.org> 1709898421 +0000
mergetag object 301876597112218c1e465ecc2b2fef6b27d5c27b
 type commit
 tag pull-riscv-to-apply-20240308-1
 tagger Alistair Francis <alistair.francis@wdc.com> 1709895703 +1000
 
 RISC-V PR for 9.0
 
 * Update $ra with current $pc in trans_cm_jalt
 * Enable SPCR for SCPI virt machine
 * Allow large kernels to boot by moving the initrd further away in RAM
 * Sync hwprobe keys with kernel
 * Named features riscv,isa, 'svade' rework
 * FIX xATP_MODE validation
 * Add missing include guard in pmu.h
 * Add SRAT and SLIT ACPI tables
 * libqos fixes and add a riscv machine
 * Add Ztso extension
 * Use 'zfa' instead of 'Zfa'
 * Update KVM exts to Linux 6.8
 * move ratified/frozen exts to non-experimental
 * Ensure mcountinhibit, mcounteren, scounteren, hcounteren are 32-bit
 * mark_vs_dirty() before loads and stores
 * Remove 'is_store' bool from load/store fns
 * Fix shift count overflow
 * Fix setipnum_le write emulation for APLIC MSI-mode
 * Fix in_clrip[x] read emulation
 * Fix privilege mode of G-stage translation for debugging
 * Fix ACPI MCFG table for virt machine
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Merge tag 'pull-riscv-to-apply-20240308-1' of https://github.com/alistair23/qemu into staging

RISC-V PR for 9.0

* Update $ra with current $pc in trans_cm_jalt
* Enable SPCR for SCPI virt machine
* Allow large kernels to boot by moving the initrd further away in RAM
* Sync hwprobe keys with kernel
* Named features riscv,isa, 'svade' rework
* FIX xATP_MODE validation
* Add missing include guard in pmu.h
* Add SRAT and SLIT ACPI tables
* libqos fixes and add a riscv machine
* Add Ztso extension
* Use 'zfa' instead of 'Zfa'
* Update KVM exts to Linux 6.8
* move ratified/frozen exts to non-experimental
* Ensure mcountinhibit, mcounteren, scounteren, hcounteren are 32-bit
* mark_vs_dirty() before loads and stores
* Remove 'is_store' bool from load/store fns
* Fix shift count overflow
* Fix setipnum_le write emulation for APLIC MSI-mode
* Fix in_clrip[x] read emulation
* Fix privilege mode of G-stage translation for debugging
* Fix ACPI MCFG table for virt machine

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# gpg: Signature made Fri 08 Mar 2024 11:10:50 GMT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20240308-1' of https://github.com/alistair23/qemu: (34 commits)
  target/riscv: fix ACPI MCFG table
  target/riscv: Fix privilege mode of G-stage translation for debugging
  hw/intc/riscv_aplic: Fix in_clrip[x] read emulation
  hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode
  target/riscv: Fix shift count overflow
  trans_rvv.c.inc: remove 'is_store' bool from load/store fns
  trans_rvv.c.inc: mark_vs_dirty() before loads and stores
  target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
  target/riscv: move ratified/frozen exts to non-experimental
  target/riscv/kvm: update KVM exts to Linux 6.8
  linux-headers: Update to Linux v6.8-rc6
  tests: riscv64: Use 'zfa' instead of 'Zfa'
  linux-user/riscv: Add Ztso extension to hwprobe
  RISC-V: Add support for Ztso
  tests/libqos: add riscv/virt machine nodes
  hw/riscv/virt.c: make aclint compatible with 'qtest' accel
  hw/riscv/virt.c: add virtio-iommu-pci hotplug support
  hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier
  hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables
  target/riscv: Add missing include guard in pmu.h
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>