commit cbc3a6a4cc675516328a2b0d3602355d68b6302d
author Artyom Tarasenko <atar4qemu@gmail.com> Tue Jun 07 18:34:49 2016 +0200
committer Artyom Tarasenko <atar4qemu@gmail.com> Wed Jan 18 22:03:44 2017 +0100
tree 837af98184dabc03c037428d2cfd8f0bf6248df6
parent 6e040755f12eba34d2fa3d56b18de32d63fea631

target-sparc: implement UA2005 GL register

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>

target/sparc/cpu.h

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index f173dd6..857e93b 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -515,6 +515,7 @@
     uint64_t bgregs[8]; /* backup for normal global registers */
     uint64_t igregs[8]; /* interrupt general registers */
     uint64_t mgregs[8]; /* mmu general registers */
+    uint64_t glregs[8 * MAXTL_MAX];
     uint64_t fprs;
     uint64_t tick_cmpr, stick_cmpr;
     CPUTimer *tick, *stick;
@@ -615,6 +616,7 @@
 target_ulong cpu_get_cwp64(CPUSPARCState *env1);
 void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
+void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
 #endif
 int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
 int cpu_cwp_dec(CPUSPARCState *env1, int cwp);