)]}'
{
  "commit": "cb4e642cfa1e6db59448978ba4c00c6f1c4fb8bd",
  "tree": "abaf3710c9fc3dda245d364669ea1dbcd11e8d1d",
  "parents": [
    "6be947bdfcaca6e87ee93a76b2ab2c5536b3b8a6"
  ],
  "author": {
    "name": "Jonathan Cameron",
    "email": "Jonathan.Cameron@huawei.com",
    "time": "Thu Mar 02 13:37:07 2023 +0000"
  },
  "committer": {
    "name": "Michael S. Tsirkin",
    "email": "mst@redhat.com",
    "time": "Tue Mar 07 12:39:00 2023 -0500"
  },
  "message": "hw/cxl: Fix endian issues in CXL RAS capability defaults / masks\n\nAs these are about to be modified, fix the endian handle for\nthis set of registers rather than making it worse.\n\nNote that CXL is currently only supported in QEMU on\nx86 (arm64 patches out of tree) so we aren\u0027t going to yet hit\nan problems with big endian. However it is good to avoid making\nthings worse for that support in the future.\n\nReviewed-by: Dave Jiang \u003cdave.jiang@intel.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nSigned-off-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nMessage-Id: \u003c20230302133709.30373-7-Jonathan.Cameron@huawei.com\u003e\nReviewed-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nReviewed-by: Fan Ni \u003cfan.ni@samsung.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3edd303a33ac9609d0af9513a2031678f8055d06",
      "old_mode": 33188,
      "old_path": "hw/cxl/cxl-component-utils.c",
      "new_id": "737b4764b9e94a3ec3c66f45e456400ed81afb48",
      "new_mode": 33188,
      "new_path": "hw/cxl/cxl-component-utils.c"
    }
  ]
}