tree a0b3bd58553a2ab6d9df2cc2be026ddf20e8ea5b
parent ffeddb979400b1580ad28acbee09b6f971c3912d
parent 3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a
author Richard Henderson <richard.henderson@linaro.org> 1719075409 -0700
committer Richard Henderson <richard.henderson@linaro.org> 1719075409 -0700
mergetag object 3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a
 type commit
 tag pull-target-arm-20240622
 tagger Peter Maydell <peter.maydell@linaro.org> 1719057852 +0100
 
 target-arm queue:
  * hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
  * hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
  * hw/intc/arm_gic: Fix deactivation of SPI lines
  * hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
  * hw/misc: Set valid access size for Exynos4210 RNG
  * hw/arm/sbsa-ref: switch to 1GHz timer frequency
  * hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
  * hw/arm/virt: allow creation of a second NonSecure UART
  * hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
  * scripts/coverity-scan/COMPONENTS.md: update component regexes
  * hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
  * hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1
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Merge tag 'pull-target-arm-20240622' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
 * hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
 * hw/intc/arm_gic: Fix deactivation of SPI lines
 * hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
 * hw/misc: Set valid access size for Exynos4210 RNG
 * hw/arm/sbsa-ref: switch to 1GHz timer frequency
 * hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
 * hw/arm/virt: allow creation of a second NonSecure UART
 * hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
 * scripts/coverity-scan/COMPONENTS.md: update component regexes
 * hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
 * hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1

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# gpg: Signature made Sat 22 Jun 2024 05:06:00 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240622' of https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
  hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1
  hw/misc: Set valid access size for Exynos4210 RNG
  hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs
  hw/arm/virt: allow creation of a second NonSecure UART
  hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01]
  hw/arm/virt: Add serial aliases in DTB
  hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
  hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
  scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibs
  scripts/coverity-scan/COMPONENTS.md: Fix monitor component
  scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to the crypto component
  scripts/coverity-scan/COMPONENTS.md: Fix 'char' component
  scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI
  hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
  hw/intc/arm_gic: Fix deactivation of SPI lines
  hw/arm/sbsa-ref: switch to 1GHz timer frequency
  hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>