)]}'
{
  "commit": "c9b07fe14d3525cd3f2fc01f46eeb3d4ed7c3603",
  "tree": "9d935afd737ae11783a8040299d1be9ad2a1693b",
  "parents": [
    "078189b327ae5c5727b51ec714d9663b1d0ca3df"
  ],
  "author": {
    "name": "Max Chou",
    "email": "max.chou@sifive.com",
    "time": "Fri Mar 22 01:09:27 2024 +0800"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Fri Mar 22 15:31:09 2024 +1000"
  },
  "message": "target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin\n\nAccording to the Zvfbfmin definition in the RISC-V BF16 extensions spec,\nthe Zvfbfmin extension only requires either the V extension or the\nZve32f extension.\n\nSigned-off-by: Max Chou \u003cmax.chou@sifive.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20240321170929.1162507-1-max.chou@sifive.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "63192ef54f3de92d00c2d217a62b577718b30f4b",
      "old_mode": 33188,
      "old_path": "target/riscv/tcg/tcg-cpu.c",
      "new_id": "b5b95e052d2df62f47608526057979cbf8d5198b",
      "new_mode": 33188,
      "new_path": "target/riscv/tcg/tcg-cpu.c"
    }
  ]
}