tree d0630eec1485a82d7c841dc65765ffde948fae11
parent 4de47793d49e70ee048e15889d4bf139e7b36ce7
author Peter Maydell <peter.maydell@linaro.org> 1331727970 +0000
committer Peter Maydell <peter.maydell@linaro.org> 1331830852 +0000

target-arm: Clear IT bits when taking exceptions in v7M

When taking an exception for an M profile core, we must clear
the IT bits. Since the IT bits are cached in env->condexec_bits
we must clear them there: writing the bits in env->uncached_cpsr
has no effect. (Reported as LP:944645.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>