commit | 800675f11742b6080e40d17b8d5f35d3a5fc5724 | [log] [tgz] |
---|---|---|
author | Maciej W. Rozycki <macro@codesourcery.com> | Mon Nov 03 18:47:45 2014 +0000 |
committer | Leon Alrae <leon.alrae@imgtec.com> | Tue Dec 16 12:45:19 2014 +0000 |
tree | 4c045b49cd4895afa41cecfc2ff3304fc1096f1e | |
parent | dfa9c2a0f4d0a0c8b2c1449ecdbb1297427e1560 [diff] |
target-mips: Correct the handling of register #72 on writes Fix an off-by-one error in `mips_cpu_gdb_write_register' for register matching how `mips_cpu_gdb_read_register' handles it. This register slot is a fake anyway, there's nothing in hardware that corresponds to it. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>