Merge tag 'pull-riscv-to-apply-20240806-2' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.1
* roms/opensbi: update to v1.5.1
* target/riscv: Add asserts for out-of-bound access
* Remove redundant insn length check for zama16b
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# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240806-2' of https://github.com/alistair23/qemu:
roms/opensbi: Update to v1.5.1
target/riscv: Add asserts for out-of-bound access
target/riscv: Relax fld alignment requirement
target/riscv: Add MXLEN check for F/D/Q applies to zama16b
target/riscv: Remove redundant insn length check for zama16b
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin b/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
index 7ec260f..b2e7400 100644
--- a/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
+++ b/pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
Binary files differ
diff --git a/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin b/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
index 090c0cf..018b473 100644
--- a/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
+++ b/pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
Binary files differ
diff --git a/roms/opensbi b/roms/opensbi
index 455de67..43cace6 160000
--- a/roms/opensbi
+++ b/roms/opensbi
@@ -1 +1 @@
-Subproject commit 455de672dd7c2aa1992df54dfb08dc11abbc1b1a
+Subproject commit 43cace6c3671e5172d0df0a8963e552bb04b7b20
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 1f5fac6..8a46124 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -47,8 +47,18 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
+ /*
+ * FLD and FSD are only guaranteed to execute atomically if the effective
+ * address is naturally aligned and XLEN≥64. Also, zama16b applies to
+ * loads and stores of no more than MXLEN bits defined in the F, D, and
+ * Q extensions.
+ */
+ if (get_xl_max(ctx) == MXL_RV32) {
+ memop |= MO_ATOM_NONE;
+ } else if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
+ } else {
+ memop |= MO_ATOM_IFALIGN;
}
decode_save_opc(ctx);
@@ -67,8 +77,12 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
+ if (get_xl_max(ctx) == MXL_RV32) {
+ memop |= MO_ATOM_NONE;
+ } else if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
+ } else {
+ memop |= MO_ATOM_IFALIGN;
}
decode_save_opc(ctx);
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index f771aa1..0222a72 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -48,7 +48,7 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
+ if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
@@ -70,7 +70,7 @@
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
+ if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 98e3806..fab5c06 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -268,7 +268,7 @@
{
bool out;
- if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
+ if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
decode_save_opc(ctx);
@@ -369,7 +369,7 @@
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
+ if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
decode_save_opc(ctx);
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 3cc0b36..e05ab06 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -204,6 +204,7 @@
}
if (env->virt_enabled) {
+ g_assert(env->priv <= PRV_S);
counter_arr = env->pmu_fixed_ctrs[1].counter_virt;
snapshot_prev = env->pmu_fixed_ctrs[1].counter_virt_prev;
} else {
@@ -212,6 +213,7 @@
}
if (new_virt) {
+ g_assert(newpriv <= PRV_S);
snapshot_new = env->pmu_fixed_ctrs[1].counter_virt_prev;
} else {
snapshot_new = env->pmu_fixed_ctrs[1].counter_prev;
@@ -242,6 +244,7 @@
}
if (env->virt_enabled) {
+ g_assert(env->priv <= PRV_S);
counter_arr = env->pmu_fixed_ctrs[0].counter_virt;
snapshot_prev = env->pmu_fixed_ctrs[0].counter_virt_prev;
} else {
@@ -250,6 +253,7 @@
}
if (new_virt) {
+ g_assert(newpriv <= PRV_S);
snapshot_new = env->pmu_fixed_ctrs[0].counter_virt_prev;
} else {
snapshot_new = env->pmu_fixed_ctrs[0].counter_prev;
