commit c5cc248b478bc21e50845ba6b2414c4a688e195f
author yang.zhang <yang.zhang@hexintek.com> Fri Jul 07 11:23:06 2023 +0800
committer Alistair Francis <alistair.francis@wdc.com> Mon Jul 10 22:29:15 2023 +1000
tree 446e7ba209b478a4f4a2cc7516d6312802748451
parent 32b2d75bf7fab6fa82dd01b2413ca14753b90973

target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly

Should set/get riscv all reg timer,i.e, time/compare/frequency/state.

Signed-off-by: Yang Zhang <yang.zhang@hexintek.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230707032306.4606-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/kvm.c

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0f932a5..c3976a5 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -99,7 +99,7 @@
 
 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
     do { \
-        int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), &reg); \
+        int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), &reg); \
         if (ret) { \
             abort(); \
         } \