commit c541b07de79daa293e9ccc07f3c98f575ad09f2a
author Alistair Francis <alistair23@gmail.com> Thu Nov 02 10:34:24 2023 +1000
committer Alistair Francis <alistair.francis@wdc.com> Tue Nov 07 11:06:02 2023 +1000
tree 30edf2d93f468a5dab652c124216dea516a96088
parent d53ead72066b1502bc3989dd11f1565d472e431d

target/riscv: cpu: Set the OpenTitan priv to 1.12.0

Set the Ibex CPU priv to 1.12.0 to ensure that smepmp/epmp is correctly
enabled.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231102003424.2003428-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/cpu.c

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d73e1da..70c0a78 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -606,7 +606,7 @@
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
-    env->priv_ver = PRIV_VERSION_1_11_0;
+    env->priv_ver = PRIV_VERSION_1_12_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
 #endif