)]}'
{
  "commit": "c4e5f9a29faadc50fed673d720199db5638fbdab",
  "tree": "4edc078271de5b9b77ceedd564afc3202d6fa77d",
  "parents": [
    "2b0612dea37802ab623e811c63a217a0b0fb9f1a",
    "e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb"
  ],
  "author": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Thu Aug 31 08:31:03 2023 -0400"
  },
  "committer": {
    "name": "Stefan Hajnoczi",
    "email": "stefanha@redhat.com",
    "time": "Thu Aug 31 08:31:03 2023 -0400"
  },
  "message": "Merge tag \u0027pull-target-arm-20230831\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm into staging\n\ntarget-arm queue:\n * Some of the preliminary patches for Cortex-A710 support\n * i.MX7 and i.MX6UL refactoring\n * Implement SRC device for i.MX7\n * Catch illegal-exception-return from EL3 with bad NSE/NS\n * Use 64-bit offsets for holding time_t differences in RTC devices\n * Model correct number of MPU regions for an505, an521, an524 boards\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmTwbukZHHBldGVyLm1h\n# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ihBD/wK8Iz0KpTAwZBDAodnSZrh\n# tQnJAvYFp8CxA4O8sZ9IeWsZh90gzsTCZi0NqUTTzvWCJfxkB7qTPdlJT5IzVxou\n# oEUk2aogSJhRA3XRJzqArXsPlnZGSYDbtwKx4VtfCvOCCH08Y7nhnFaRj1oFnR4Q\n# 0PE/8YtGXTBxLHrO8U3tomg7zElzOUP8ZVZtb30BOyw1jtfSD03IZR8dzpA43u1E\n# Hh418WvVekmwFoFNh8yUeHzbyXMZufzvbJPuDGJ8pPWwIpvSG6chOnKF8jZll+Ur\n# DqOsDkGlQgcBR2QwYfSPClrEkX8yahJ95PBfM6giG+DQC7OiElqXqTiUGZcpgUVo\n# uSUbzS4YPsxCnyVV6SBXV+f/8hdXBxOSHTgl7OAFa8X9OwWwspxHJ/v2o/2ibnUT\n# hTTkFp/w1nQwVEN8xf1DOUpm/J2Wr8UeH4f776daSrfKAol2BKbHb8dOgGLQCwqb\n# G+iDcE4bkzRqly6f+uVk8xSEZDd9P1NYoxKV+gNlV1dTspdHVpTC+rXMa8dRw5hI\n# 4KgaAslj++Xa229xkjORXCJ1cICRIebYg7+SjvTtGBYsFV7plsCcYb/R9yLmhVCf\n# fKHKKaYe9sQJ82apOIkTc+nnW8BQQx6XUmU/A//iZ8JGLk6DpJcZ8f1m/2rVZTsl\n# 9+lsmpBf4w+uR4o+Womhfw\u003d\u003d\n# \u003dMFh3\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Thu 31 Aug 2023 06:43:53 EDT\n# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE\n# gpg:                issuer \"peter.maydell@linaro.org\"\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@gmail.com\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@chiark.greenend.org.uk\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpeter@archaic.org.uk\u003e\" [unknown]\n# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE\n\n* tag \u0027pull-target-arm-20230831\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits)\n  hw/arm: Set number of MPU regions correctly for an505, an521, an524\n  hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties\n  target/arm: Do all \"ARM_FEATURE_X implies Y\" checks in post_init\n  rtc: Use time_t for passing and returning time offsets\n  hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference\n  hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec\n  hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()\n  target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS\n  Add i.MX7 SRC device implementation\n  Add i.MX7 missing TZ devices and memory regions\n  Refactor i.MX7 processor code\n  Add i.MX6UL missing devices.\n  Refactor i.MX6UL processor code\n  Remove i.MX7 IOMUX GPR device from i.MX6UL\n  target/arm: properly document FEAT_CRC32\n  target/arm: Implement FEAT_HPDS2 as a no-op\n  target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)\n  target/arm: Apply access checks to neoverse-v1 special registers\n  target/arm: Apply access checks to neoverse-n1 special registers\n  target/arm: Introduce make_ccsidr64\n  ...\n\nSigned-off-by: Stefan Hajnoczi \u003cstefanha@redhat.com\u003e\n",
  "tree_diff": []
}