)]}'
{
  "commit": "c2fae597099ef6ff81ca63d69ee28eddb982d894",
  "tree": "888a0048d2b790704db53f924cbe6a04607634ba",
  "parents": [
    "e0ca100425853aa362acefeb027800d952fb222d"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue Aug 19 15:56:58 2025 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Sat Aug 30 16:37:23 2025 +0100"
  },
  "message": "target/arm: Correct condition of aa64_atomics feature function\n\nThe ARMv8.1-Atomics feature (renamed FEAT_LSE in more modern versions\nof the Arm ARM) has always ben indicated by ID_AA64ISAR0.ATOMIC being\n0b0010 or greater; 0b0001 is a reserved unused value.\n\nWe were incorrectly checking for !\u003d 0; this had no harmful effects\nbecause all the CPUs set their value for this field to either 0\n(for not having the feature) or 2 (if they do have it), but it\u0027s\nbetter to match what the architecture specifies here.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20250819145659.2165160-1-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "41511d08350b0b9fe5ce2da7e5a188e518ba0a37",
      "old_mode": 33188,
      "old_path": "target/arm/cpu-features.h",
      "new_id": "d48754bcf27bf667851fc0f023c83600d6941e54",
      "new_mode": 33188,
      "new_path": "target/arm/cpu-features.h"
    }
  ]
}