)]}'
{
  "commit": "c1d5ec3a2f4bbc9fdc120ba5697e8ad89e682e45",
  "tree": "aef366ea39211bd563a2ce9d4bcc05270b80c00d",
  "parents": [
    "b18e3f0e2d0f301952ff3ae4cb73d0e9eb4ee697"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "daniel.barboza@oss.qualcomm.com",
    "time": "Wed Jul 01 09:11:09 2026 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Thu Jul 09 14:58:02 2026 +1000"
  },
  "message": "hw/riscv/riscv-iommu.c: check for reserved PTE bits\n\nWe need to fault if reserved PTE bits (60:54) are set.\n\nFixes: 0c54acb8243d (\"hw/riscv: add RISC-V IOMMU base emulation\")\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3554\nSigned-off-by: Daniel Henrique Barboza \u003cdaniel.barboza@oss.qualcomm.com\u003e\nReviewed-by: Nutty Liu \u003cnutty.liu@hotmail.com\u003e\nReviewed-by: Chao Liu \u003cchao.liu.zevorn@gmail.com\u003e\nMessage-ID: \u003c20260701121111.537654-2-daniel.barboza@oss.qualcomm.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7f94ce152e337a451078386bdefe9d6e7731412b",
      "old_mode": 33188,
      "old_path": "hw/riscv/riscv-iommu.c",
      "new_id": "6665ad9f7cd3b501af936688562e010d0b346bd8",
      "new_mode": 33188,
      "new_path": "hw/riscv/riscv-iommu.c"
    }
  ]
}