Merge tag 'pull-ci-20230607' of https://gitlab.com/rth7680/qemu into staging
Fix TCI regressions vs Int128
Fix Arm build vs --disable-tcg
Fix iotest 194.
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# gpg: Signature made Wed 07 Jun 2023 08:39:22 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-ci-20230607' of https://gitlab.com/rth7680/qemu:
iotests: fix 194: filter out racy postcopy-active event
gitlab: Add cross-arm64-kvm-only
target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG
tcg/tci: Adjust call-clobbered regs for int128_t
tcg/tci: Adjust passing of MemOpIdx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 61b8ac8..1e0e6c7 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -29,6 +29,14 @@
variables:
IMAGE: debian-arm64-cross
+cross-arm64-kvm-only:
+ extends: .cross_accel_build_job
+ needs:
+ job: arm64-debian-cross-container
+ variables:
+ IMAGE: debian-arm64-cross
+ EXTRA_CONFIGURE_OPTS: --disable-tcg --without-default-features
+
cross-i386-user:
extends:
- .cross_user_build_job
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index b2dc223..37bcb17 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -14,8 +14,9 @@
#include "cpu.h"
#include "internals.h"
#include "idau.h"
-#include "tcg/oversized-guest.h"
-
+#ifdef CONFIG_TCG
+# include "tcg/oversized-guest.h"
+#endif
typedef struct S1Translate {
ARMMMUIdx in_mmu_idx;
diff --git a/tcg/tci.c b/tcg/tci.c
index 813572f..4640902 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -106,7 +106,7 @@
{
*r0 = extract32(insn, 8, 4);
*r1 = extract32(insn, 12, 4);
- *m2 = extract32(insn, 20, 12);
+ *m2 = extract32(insn, 16, 16);
}
static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2)
@@ -141,15 +141,6 @@
*c3 = extract32(insn, 20, 4);
}
-static void tci_args_rrrm(uint32_t insn,
- TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3)
-{
- *r0 = extract32(insn, 8, 4);
- *r1 = extract32(insn, 12, 4);
- *r2 = extract32(insn, 16, 4);
- *m3 = extract32(insn, 20, 12);
-}
-
static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
TCGReg *r2, uint8_t *i3, uint8_t *i4)
{
@@ -929,8 +920,9 @@
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
taddr = tci_uint64(regs[r2], regs[r1]);
+ oi = regs[r3];
}
do_ld_i32:
regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
@@ -941,8 +933,9 @@
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = (uint32_t)regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
taddr = (uint32_t)regs[r2];
+ oi = regs[r3];
}
goto do_ld_i64;
case INDEX_op_qemu_ld_a64_i64:
@@ -972,8 +965,9 @@
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
taddr = tci_uint64(regs[r2], regs[r1]);
+ oi = regs[r3];
}
do_st_i32:
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
@@ -985,9 +979,10 @@
tmp64 = regs[r0];
taddr = (uint32_t)regs[r1];
} else {
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
tmp64 = tci_uint64(regs[r1], regs[r0]);
taddr = (uint32_t)regs[r2];
+ oi = regs[r3];
}
goto do_st_i64;
case INDEX_op_qemu_st_a64_i64:
@@ -1293,9 +1288,10 @@
op_name, str_r(r0), str_r(r1), oi);
break;
case 3:
- tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x",
- op_name, str_r(r0), str_r(r1), str_r(r2), oi);
+ tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
+ info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
+ op_name, str_r(r0), str_r(r1),
+ str_r(r2), str_r(r3));
break;
case 4:
tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index c9516a5..0037f90 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -179,8 +179,6 @@
}
static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R2,
- TCG_REG_R3,
TCG_REG_R4,
TCG_REG_R5,
TCG_REG_R6,
@@ -193,6 +191,9 @@
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
+ /* Either 2 or 4 of these are call clobbered, so use them last. */
+ TCG_REG_R3,
+ TCG_REG_R2,
TCG_REG_R1,
TCG_REG_R0,
};
@@ -331,11 +332,11 @@
{
tcg_insn_unit insn = 0;
- tcg_debug_assert(m2 == extract32(m2, 0, 12));
+ tcg_debug_assert(m2 == extract32(m2, 0, 16));
insn = deposit32(insn, 0, 8, op);
insn = deposit32(insn, 8, 4, r0);
insn = deposit32(insn, 12, 4, r1);
- insn = deposit32(insn, 20, 12, m2);
+ insn = deposit32(insn, 16, 16, m2);
tcg_out32(s, insn);
}
@@ -392,20 +393,6 @@
tcg_out32(s, insn);
}
-static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op,
- TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3)
-{
- tcg_insn_unit insn = 0;
-
- tcg_debug_assert(m3 == extract32(m3, 0, 12));
- insn = deposit32(insn, 0, 8, op);
- insn = deposit32(insn, 8, 4, r0);
- insn = deposit32(insn, 12, 4, r1);
- insn = deposit32(insn, 16, 4, r2);
- insn = deposit32(insn, 20, 12, m3);
- tcg_out32(s, insn);
-}
-
static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0,
TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4)
{
@@ -860,7 +847,8 @@
if (TCG_TARGET_REG_BITS == 64) {
tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
} else {
- tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]);
+ tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], TCG_REG_TMP);
}
break;
case INDEX_op_qemu_ld_a64_i64:
@@ -947,11 +935,11 @@
/*
* The interpreter "registers" are in the local stack frame and
* cannot be clobbered by the called helper functions. However,
- * the interpreter assumes a 64-bit return value and assigns to
+ * the interpreter assumes a 128-bit return value and assigns to
* the return value registers.
*/
tcg_target_call_clobber_regs =
- MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS);
+ MAKE_64BIT_MASK(TCG_REG_R0, 128 / TCG_TARGET_REG_BITS);
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
diff --git a/tests/qemu-iotests/194 b/tests/qemu-iotests/194
index 6889437..c0ce82d 100755
--- a/tests/qemu-iotests/194
+++ b/tests/qemu-iotests/194
@@ -74,6 +74,11 @@
while True:
event1 = source_vm.event_wait('MIGRATION')
+ if event1['data']['status'] == 'postcopy-active':
+ # This event is racy, it depends do we really do postcopy or bitmap
+ # was migrated during downtime (and no data to migrate in postcopy
+ # phase). So, don't log it.
+ continue
iotests.log(event1, filters=[iotests.filter_qmp_event])
if event1['data']['status'] in ('completed', 'failed'):
iotests.log('Gracefully ending the `drive-mirror` job on source...')
diff --git a/tests/qemu-iotests/194.out b/tests/qemu-iotests/194.out
index 4e6df15..376ed1d 100644
--- a/tests/qemu-iotests/194.out
+++ b/tests/qemu-iotests/194.out
@@ -14,7 +14,6 @@
{"return": {}}
{"data": {"status": "setup"}, "event": "MIGRATION", "timestamp": {"microseconds": "USECS", "seconds": "SECS"}}
{"data": {"status": "active"}, "event": "MIGRATION", "timestamp": {"microseconds": "USECS", "seconds": "SECS"}}
-{"data": {"status": "postcopy-active"}, "event": "MIGRATION", "timestamp": {"microseconds": "USECS", "seconds": "SECS"}}
{"data": {"status": "completed"}, "event": "MIGRATION", "timestamp": {"microseconds": "USECS", "seconds": "SECS"}}
Gracefully ending the `drive-mirror` job on source...
{"return": {}}
