commit befbb3ced5869003ee2e806c4f36e306918d2374
author Richard Henderson <rth@twiddle.net> Fri Oct 14 15:50:25 2016 -0500
committer Richard Henderson <rth@twiddle.net> Tue Jan 10 08:03:59 2017 -0800
tree d85e17ac1cedf5f7ae5d3b4f932b887957d086b8
parent 78fdbfb94616f0391834d2eccabd16ea29e37da5

tcg/mips: Implement field extraction opcodes

Signed-off-by: Richard Henderson <rth@twiddle.net>

tcg/mips/tcg-target.h

diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index fcc2986..92d203a 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -158,7 +158,7 @@
 #define TCG_TARGET_HAS_movcond_i32      use_movnz_instructions
 #define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions
 #define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions
-#define TCG_TARGET_HAS_extract_i32      0
+#define TCG_TARGET_HAS_extract_i32      use_mips32r2_instructions
 #define TCG_TARGET_HAS_sextract_i32     0
 #define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions
 #define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions
@@ -170,6 +170,8 @@
 #define TCG_TARGET_HAS_bswap32_i64      use_mips32r2_instructions
 #define TCG_TARGET_HAS_bswap64_i64      use_mips32r2_instructions
 #define TCG_TARGET_HAS_deposit_i64      use_mips32r2_instructions
+#define TCG_TARGET_HAS_extract_i64      use_mips32r2_instructions
+#define TCG_TARGET_HAS_sextract_i64     0
 #define TCG_TARGET_HAS_ext8s_i64        use_mips32r2_instructions
 #define TCG_TARGET_HAS_ext16s_i64       use_mips32r2_instructions
 #define TCG_TARGET_HAS_rot_i64          use_mips32r2_instructions

tcg/mips/tcg-target.inc.c

diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 5b2fe98..24c4949 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -2051,6 +2051,13 @@
         tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
                          args[3] + args[4] - 1, args[3]);
         break;
+    case INDEX_op_extract_i32:
+        tcg_out_opc_bf(s, OPC_EXT, a0, a1, a2 + args[3] - 1, a2);
+        break;
+    case INDEX_op_extract_i64:
+        tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
+                         a2 + args[3] - 1, a2);
+        break;
 
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
@@ -2155,6 +2162,7 @@
     { INDEX_op_ext16s_i32, { "r", "rZ" } },
 
     { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
+    { INDEX_op_extract_i32, { "r", "r" } },
 
     { INDEX_op_brcond_i32, { "rZ", "rZ" } },
 #if use_mips32r6_instructions
@@ -2224,6 +2232,7 @@
     { INDEX_op_extrh_i64_i32, { "r", "rZ" } },
 
     { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+    { INDEX_op_extract_i64, { "r", "r" } },
 
     { INDEX_op_brcond_i64, { "rZ", "rZ" } },
 #if use_mips32r6_instructions