commit bd1ad92ccfa48c44f001ebea17633ef61ff62642
author Sven Schnelle <svens@stackframe.org> Thu Mar 21 19:42:27 2024 +0100
committer Richard Henderson <richard.henderson@linaro.org> Wed Mar 27 12:15:25 2024 -1000
tree c32f0d03291dd7164cb0dc09d1e8f0724fe47bd7
parent 578b8132b2666f7168b16422ac566684918a371e

target/hppa: Fix ADD/SUB trap on overflow for narrow mode

Fixes: c53e401ed9ff ("target/hppa: Remove TARGET_REGISTER_BITS")
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240321184228.611897-2-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa/translate.c

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 2cb9195..ceb739c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1126,6 +1126,9 @@
     if (is_tsv || cond_need_sv(c)) {
         sv = do_add_sv(ctx, dest, in1, in2);
         if (is_tsv) {
+            if (!d) {
+                tcg_gen_ext32s_i64(sv, sv);
+            }
             /* ??? Need to include overflow from shift.  */
             gen_helper_tsv(tcg_env, sv);
         }
@@ -1217,6 +1220,9 @@
     if (is_tsv || cond_need_sv(c)) {
         sv = do_sub_sv(ctx, dest, in1, in2);
         if (is_tsv) {
+            if (!d) {
+                tcg_gen_ext32s_i64(sv, sv);
+            }
             gen_helper_tsv(tcg_env, sv);
         }
     }