)]}'
{
  "commit": "bc63c99ef8184aaf2f6ea488e5fc9cfa391b871e",
  "tree": "ee678d21ddcc219a56da6722d22eb49ebfaf12f5",
  "parents": [
    "7b165fa164022b756c2b001d0a1525f98199d3ac"
  ],
  "author": {
    "name": "Dave Jiang",
    "email": "dave.jiang@intel.com",
    "time": "Mon Sep 04 14:28:04 2023 +0100"
  },
  "committer": {
    "name": "Michael Tokarev",
    "email": "mjt@tls.msk.ru",
    "time": "Thu Sep 21 11:31:18 2023 +0300"
  },
  "message": "hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS\n\nAccording to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth\nInformation Structure, if the \"Entry Base Unit\" is 1024 for BW and the\nmatrix entry has the value of 100, the BW is 100 GB/s. So the\nentry_base_unit should be changed from 1000 to 1024 given the comment notes\nit\u0027s 16GB/s for .latency_bandwidth.\n\nFixes: 882877fc359d (\"hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE\")\nSigned-off-by: Dave Jiang \u003cdave.jiang@intel.com\u003e\nSigned-off-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nReviewed-by: Fan Ni \u003cfan.ni@samsung.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nSigned-off-by: Michael Tokarev \u003cmjt@tls.msk.ru\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9159f48a8cb7c514169d1ddc671b4828a4c6b587",
      "old_mode": 33188,
      "old_path": "hw/pci-bridge/cxl_upstream.c",
      "new_id": "2b9cf0cc97949329ad800251b13ebb914da31ed9",
      "new_mode": 33188,
      "new_path": "hw/pci-bridge/cxl_upstream.c"
    }
  ]
}