commit | 53593e90d13264dc88b3281ddf75ceaa641df05a | [log] [tgz] |
---|---|---|
author | Max Filippov <jcmvbkbc@gmail.com> | Wed Dec 05 07:15:23 2012 +0400 |
committer | Blue Swirl <blauwirbel@gmail.com> | Sat Dec 08 18:48:26 2012 +0000 |
tree | 1012b37c8cf0e93b93130060cddbb8d4f7028f6b | |
parent | fe0bd475aa31e60674f7f53b85dc293108026202 [diff] |
target-xtensa: better control rsr/wsr/xsr access to SRs There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs, and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal opcode exception on illegal access to these SRs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>