accel/tcg: Replace CPUState.env_ptr with cpu_env()
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 46af657..3233308 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2871,7 +2871,7 @@
static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAlphaState *env = cpu->env_ptr;
+ CPUAlphaState *env = cpu_env(cpu);
int64_t bound;
ctx->tbflags = ctx->base.tb->flags;
@@ -2917,7 +2917,7 @@
static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAlphaState *env = cpu->env_ptr;
+ CPUAlphaState *env = cpu_env(cpu);
uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
ctx->base.pc_next += 4;
diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-target.h
index 629d75c..19438ed 100644
--- a/target/arm/common-semi-target.h
+++ b/target/arm/common-semi-target.h
@@ -38,7 +38,7 @@
static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
{
- return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
+ return nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cpu_env(cs));
}
static inline bool is_64bit_semihosting(CPUArchState *env)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d48a70c..36797c2 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -80,7 +80,7 @@
{
/* The program counter is always up to date with CF_PCREL. */
if (!(tb_cflags(tb) & CF_PCREL)) {
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
/*
* It's OK to look at env for the current mode here, because it's
* never possible for an AArch64 TB to chain to an AArch32 TB.
@@ -97,7 +97,7 @@
const TranslationBlock *tb,
const uint64_t *data)
{
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
if (is_a64(env)) {
if (tb_cflags(tb) & CF_PCREL) {
@@ -560,7 +560,7 @@
unsigned int cur_el, bool secure,
uint64_t hcr_el2)
{
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
bool pstate_unmasked;
bool unmasked = false;
@@ -690,7 +690,7 @@
static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
uint32_t cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8362078..74fbb6e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10297,7 +10297,7 @@
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure)
{
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
bool rw;
bool scr;
bool hcr;
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 66a010e..10e8dcf 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -13982,7 +13982,7 @@
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
ARMCPU *arm_cpu = env_archcpu(env);
CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb);
int bound, core_mmu_idx;
@@ -14089,7 +14089,7 @@
static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *s = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
uint64_t pc = s->base.pc_next;
uint32_t insn;
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 2524d8f..48927fb 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -9089,7 +9089,7 @@
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cs->env_ptr;
+ CPUARMState *env = cpu_env(cs);
ARMCPU *cpu = env_archcpu(env);
CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb);
uint32_t condexec, core_mmu_idx;
@@ -9317,7 +9317,7 @@
static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
uint32_t pc = dc->base.pc_next;
unsigned int insn;
@@ -9407,7 +9407,7 @@
static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu->env_ptr;
+ CPUARMState *env = cpu_env(cpu);
uint32_t pc = dc->base.pc_next;
uint32_t insn;
bool is_16bit;
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 8d67570..cdffa04 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2657,7 +2657,7 @@
static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUAVRState *env = cs->env_ptr;
+ CPUAVRState *env = cpu_env(cs);
uint32_t tb_flags = ctx->base.tb->flags;
ctx->cs = cs;
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 395ba12..b3974ba 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -2948,7 +2948,7 @@
static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUCRISState *env = cs->env_ptr;
+ CPUCRISState *env = cpu_env(cs);
uint32_t tb_flags = dc->base.tb->flags;
uint32_t pc_start;
@@ -3006,7 +3006,7 @@
static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUCRISState *env = cs->env_ptr;
+ CPUCRISState *env = cpu_env(cs);
unsigned int insn_len;
/* Pretty disas. */
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 012c3c6..663b7bb 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -1053,7 +1053,7 @@
CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- HexagonCPU *hex_cpu = env_archcpu(cs->env_ptr);
+ HexagonCPU *hex_cpu = env_archcpu(cpu_env(cs));
uint32_t hex_flags = dcbase->tb->flags;
ctx->mem_idx = MMU_USER_IDX;
@@ -1094,7 +1094,7 @@
static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUHexagonState *env = cpu->env_ptr;
+ CPUHexagonState *env = cpu_env(cpu);
decode_and_translate_packet(env, ctx);
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 520fd31..350485f 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -335,7 +335,7 @@
synchronous across all processors. */
static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
{
- CPUHPPAState *env = cpu->env_ptr;
+ CPUHPPAState *env = cpu_env(cpu);
target_ulong addr = (target_ulong) data.target_ptr;
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 0c67d71..9f3ba9f 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3450,7 +3450,7 @@
#ifndef CONFIG_USER_ONLY
if (ctx->tb_flags & PSW_C) {
- CPUHPPAState *env = ctx->cs->env_ptr;
+ CPUHPPAState *env = cpu_env(ctx->cs);
int type = hppa_artype_for_page(env, ctx->base.pc_next);
/* If we could not find a TLB entry, then we need to generate an
ITLB miss exception so the kernel will provide it.
@@ -4119,7 +4119,7 @@
static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUHPPAState *env = cs->env_ptr;
+ CPUHPPAState *env = cpu_env(cs);
DisasJumpType ret;
int i, n;
diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c
index 066a173..fb76986 100644
--- a/target/i386/nvmm/nvmm-all.c
+++ b/target/i386/nvmm/nvmm-all.c
@@ -78,7 +78,7 @@
static void
nvmm_set_registers(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
@@ -215,7 +215,7 @@
static void
nvmm_get_registers(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
@@ -340,7 +340,7 @@
static bool
nvmm_can_take_int(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
struct nvmm_machine *mach = get_nvmm_mach();
@@ -387,7 +387,7 @@
static void
nvmm_vcpu_pre_run(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
@@ -473,8 +473,8 @@
nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit)
{
AccelCPUState *qcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
uint64_t tpr;
env->eflags = exit->exitstate.rflags;
@@ -645,7 +645,7 @@
nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu,
struct nvmm_vcpu_exit *exit)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
int ret = 0;
qemu_mutex_lock_iothread();
@@ -678,11 +678,11 @@
static int
nvmm_vcpu_loop(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
struct nvmm_machine *mach = get_nvmm_mach();
AccelCPUState *qcpu = cpu->accel;
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
struct nvmm_vcpu_exit *exit = vcpu->exit;
int ret;
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index af1878c..7d76f15 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -1595,7 +1595,7 @@
*/
static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
bool first = true;
X86DecodedInsn decode;
X86DecodeFunc decode_func = decode_root;
diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index 226689a..5b86f43 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -597,7 +597,7 @@
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- CPUX86State *env = cs->env_ptr;
+ CPUX86State *env = cpu_env(cs);
TranslateResult out;
TranslateFault err;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 5c3a508..2c6a12c 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -51,7 +51,7 @@
{
/* The instruction pointer is always up to date with CF_PCREL. */
if (!(tb_cflags(tb) & CF_PCREL)) {
- CPUX86State *env = cs->env_ptr;
+ CPUX86State *env = cpu_env(cs);
env->eip = tb->pc - tb->cs_base;
}
}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 4db91d1..4f12873 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3079,7 +3079,7 @@
be stopped. Return the next pc value */
static bool disas_insn(DisasContext *s, CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
int b, prefixes;
int shift;
MemOp ot, aflag, dflag;
@@ -6918,7 +6918,7 @@
static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
uint32_t flags = dc->base.tb->flags;
uint32_t cflags = tb_cflags(dc->base.tb);
int cpl = (flags >> HF_CPL_SHIFT) & 3;
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 3de0dc1..df3aba2 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -300,7 +300,7 @@
/* X64 Extended Control Registers */
static void whpx_set_xcrs(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
WHV_REGISTER_VALUE xcr0;
@@ -321,7 +321,7 @@
static int whpx_set_tsc(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
@@ -382,8 +382,8 @@
{
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
struct whpx_register_set vcxt;
HRESULT hr;
int idx;
@@ -556,7 +556,7 @@
static int whpx_get_tsc(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
WHV_REGISTER_VALUE tsc_val;
HRESULT hr;
@@ -576,7 +576,7 @@
/* X64 Extended Control Registers */
static void whpx_get_xcrs(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
WHV_REGISTER_VALUE xcr0;
@@ -601,8 +601,8 @@
{
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
struct whpx_register_set vcxt;
uint64_t tpr, apic_base;
HRESULT hr;
@@ -1400,7 +1400,7 @@
{
if (cpu->vcpu_dirty) {
/* The CPU registers have been modified by other parts of QEMU. */
- CPUArchState *env = (CPUArchState *)(cpu->env_ptr);
+ CPUArchState *env = cpu_env(cpu);
return env->eip;
} else if (exit_context_valid) {
/*
@@ -1439,7 +1439,7 @@
static int whpx_handle_halt(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
+ CPUX86State *env = cpu_env(cpu);
int ret = 0;
qemu_mutex_lock_iothread();
@@ -1460,8 +1460,8 @@
HRESULT hr;
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
int irq;
uint8_t tpr;
WHV_X64_PENDING_INTERRUPTION_REGISTER new_int;
@@ -1582,8 +1582,8 @@
static void whpx_vcpu_post_run(CPUState *cpu)
{
AccelCPUState *vcpu = cpu->accel;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
env->eflags = vcpu->exit_ctx.VpContext.Rflags;
@@ -1606,8 +1606,8 @@
static void whpx_vcpu_process_async_events(CPUState *cpu)
{
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
AccelCPUState *vcpu = cpu->accel;
if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
@@ -2147,8 +2147,8 @@
struct whpx_state *whpx = &whpx_global;
AccelCPUState *vcpu = NULL;
Error *local_error = NULL;
- CPUX86State *env = cpu->env_ptr;
X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
UINT64 freq = 0;
int ret;
@@ -2245,7 +2245,7 @@
cpu->vcpu_dirty = true;
cpu->accel = vcpu;
max_vcpu_index = max(max_vcpu_index, cpu->cpu_index);
- qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr);
+ qemu_add_vm_change_state_handler(whpx_cpu_update_state, env);
return 0;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 47598a9..21f4db6 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -117,7 +117,7 @@
CPUState *cs)
{
int64_t bound;
- CPULoongArchState *env = cs->env_ptr;
+ CPULoongArchState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
@@ -282,7 +282,7 @@
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPULoongArchState *env = cs->env_ptr;
+ CPULoongArchState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 587fe36..4d0110d 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5990,7 +5990,7 @@
static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUM68KState *env = cpu->env_ptr;
+ CPUM68KState *env = cpu_env(cpu);
dc->env = env;
dc->pc = dc->base.pc_first;
@@ -6021,7 +6021,7 @@
static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUM68KState *env = cpu->env_ptr;
+ CPUM68KState *env = cpu_env(cpu);
uint16_t insn = read_im16(env, dc);
opcode_table[insn](env, dc, insn);
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index bb17821..49bfb4a 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1630,7 +1630,7 @@
static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
- CPUMBState *env = cs->env_ptr;
+ CPUMBState *env = cpu_env(cs);
uint32_t ir;
/* TODO: This should raise an exception, not terminate qemu. */
diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c
index f3735df..b3e4e49 100644
--- a/target/mips/tcg/sysemu/mips-semi.c
+++ b/target/mips/tcg/sysemu/mips-semi.c
@@ -126,7 +126,7 @@
static void uhi_cb(CPUState *cs, uint64_t ret, int err)
{
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
#define E(N) case E##N: err = UHI_E##N; break
@@ -167,7 +167,7 @@
QEMU_BUILD_BUG_ON(sizeof(UHIStat) < sizeof(struct gdb_stat));
if (!err) {
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
target_ulong addr = env->active_tc.gpr[5];
UHIStat *dst = lock_user(VERIFY_WRITE, addr, sizeof(UHIStat), 1);
struct gdb_stat s;
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6d5a552..13e43fa 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15376,7 +15376,7 @@
static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
ctx->saved_pc = -1;
@@ -15447,7 +15447,7 @@
static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPUMIPSState *env = cs->env_ptr;
+ CPUMIPSState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
int insn_bytes;
int is_slot;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 93ded65..e806623 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -944,7 +944,7 @@
static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUNios2State *env = cs->env_ptr;
+ CPUNios2State *env = cpu_env(cs);
Nios2CPU *cpu = env_archcpu(env);
int page_insns;
@@ -970,7 +970,7 @@
static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUNios2State *env = cs->env_ptr;
+ CPUNios2State *env = cpu_env(cs);
const Nios2Instruction *instr;
uint32_t code, pc;
uint8_t op;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 1b4df1c..ecff441 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1525,7 +1525,7 @@
static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
- CPUOpenRISCState *env = cs->env_ptr;
+ CPUOpenRISCState *env = cpu_env(cs);
int bound;
dc->mem_idx = cpu_mmu_index(env, false);
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 99099cb..7926114 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -3189,7 +3189,7 @@
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
uint32_t insn;
/* Restore state and reload the insn we executed, for filling in DSISR. */
@@ -3220,7 +3220,7 @@
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
switch (env->excp_model) {
#if defined(TARGET_PPC64)
@@ -3264,7 +3264,7 @@
void ppc_cpu_debug_excp_handler(CPUState *cs)
{
#if defined(TARGET_PPC64)
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
if (env->insns_flags2 & PPC2_ISA207S) {
if (cs->watchpoint_hit) {
@@ -3286,7 +3286,7 @@
bool ppc_cpu_debug_check_breakpoint(CPUState *cs)
{
#if defined(TARGET_PPC64)
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
if (env->insns_flags2 & PPC2_ISA207S) {
target_ulong priv;
@@ -3313,7 +3313,7 @@
bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
{
#if defined(TARGET_PPC64)
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
if (env->insns_flags2 & PPC2_ISA207S) {
if (wp == env->dawr0_watchpoint) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e20a1be..329da4d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7320,7 +7320,7 @@
static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
uint32_t hflags = ctx->base.tb->flags;
ctx->spr_cb = env->spr_cb;
@@ -7384,7 +7384,7 @@
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = cs->env_ptr;
+ CPUPPCState *env = cpu_env(cs);
target_ulong pc;
uint32_t insn;
bool ok;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2ad5192..f0be79b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1074,7 +1074,7 @@
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUState *cpu = ctx->cs;
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cpu_env(cpu);
return cpu_ldl_code(env, pc);
}
@@ -1166,7 +1166,7 @@
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cs->env_ptr;
+ CPURISCVState *env = cpu_env(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t tb_flags = ctx->base.tb->flags;
@@ -1219,7 +1219,7 @@
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cpu_env(cpu);
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
ctx->ol = ctx->xl;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 5155994..2e7a736 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -183,12 +183,9 @@
static void rx_cpu_init(Object *obj)
{
- CPUState *cs = CPU(obj);
RXCPU *cpu = RX_CPU(obj);
- CPURXState *env = &cpu->env;
cpu_set_cpustate_pointers(cpu);
- cs->env_ptr = env;
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 9fd4d36..f886083 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2200,7 +2200,7 @@
static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
- CPURXState *env = cs->env_ptr;
+ CPURXState *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->env = env;
ctx->tb_flags = ctx->base.tb->flags;
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 22f4397..4bae150 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6463,7 +6463,7 @@
static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPUS390XState *env = cs->env_ptr;
+ CPUS390XState *env = cpu_env(cs);
DisasContext *dc = container_of(dcbase, DisasContext, base);
dc->base.is_jmp = translate_one(env, dc);
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index a663335..ada41ba 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -29,7 +29,7 @@
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- CPUSH4State *env = cs->env_ptr;
+ CPUSH4State *env = cpu_env(cs);
env->tea = addr;
switch (access_type) {
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 30e3ea5..cbd8dfc 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2179,7 +2179,7 @@
static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUSH4State *env = cs->env_ptr;
+ CPUSH4State *env = cpu_env(cs);
uint32_t tbflags;
int bound;
@@ -2236,7 +2236,7 @@
static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
- CPUSH4State *env = cs->env_ptr;
+ CPUSH4State *env = cpu_env(cs);
DisasContext *ctx = container_of(dcbase, DisasContext, base);
#ifdef CONFIG_USER_ONLY
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 71b48cb..f92ff80 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5568,7 +5568,7 @@
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUSPARCState *env = cs->env_ptr;
+ CPUSPARCState *env = cpu_env(cs);
int bound;
dc->pc = dc->base.pc_first;
@@ -5625,7 +5625,7 @@
static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUSPARCState *env = cs->env_ptr;
+ CPUSPARCState *env = cpu_env(cs);
unsigned int insn;
insn = translator_ldl(env, &dc->base, dc->pc);
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 114fdda..dd812ec 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8366,7 +8366,7 @@
CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUTriCoreState *env = cs->env_ptr;
+ CPUTriCoreState *env = cpu_env(cs);
ctx->mem_idx = cpu_mmu_index(env, false);
uint32_t tb_flags = (uint32_t)ctx->base.tb->flags;
@@ -8411,7 +8411,7 @@
static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPUTriCoreState *env = cpu->env_ptr;
+ CPUTriCoreState *env = cpu_env(cpu);
uint16_t insn_lo;
bool is_16bit;
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index fca1b9a..54bee7d 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1140,7 +1140,7 @@
CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
uint32_t tb_flags = dc->base.tb->flags;
dc->config = env->config;
@@ -1180,7 +1180,7 @@
static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUXtensaState *env = cpu->env_ptr;
+ CPUXtensaState *env = cpu_env(cpu);
target_ulong page_start;
/* These two conditions only apply to the first insn in the TB,
