commit b2d9eda5d473fa7251319a368b0ee72d75218aed
author Aurelien Jarno <aurelien@aurel32.net> Thu Jan 13 08:20:39 2011 +0100
committer Aurelien Jarno <aurelien@aurel32.net> Sun Jan 16 13:19:20 2011 +0100
tree 72f57871efe63fd03f00ffcde050b1475a37fa39
parent 2411fde9a41323310d472dd352006989f30049b2

target-sh4: implement negc using TCG

Using setcond it's now possible to generate a relatively short negc
instruction in TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target-sh4/helper.h

diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 4e595c8..2e52768 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -17,7 +17,6 @@
 DEF_HELPER_2(addc, i32, i32, i32)
 DEF_HELPER_2(subv, i32, i32, i32)
 DEF_HELPER_2(subc, i32, i32, i32)
-DEF_HELPER_1(negc, i32, i32)
 DEF_HELPER_2(div1, i32, i32, i32)
 DEF_HELPER_2(macl, void, i32, i32)
 DEF_HELPER_2(macw, void, i32, i32)

target-sh4/op_helper.c

diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 9d7652f..30f9842 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -379,21 +379,6 @@
     }
 }
 
-uint32_t helper_negc(uint32_t arg)
-{
-    uint32_t temp;
-
-    temp = -arg;
-    arg = temp - (env->sr & SR_T);
-    if (0 < temp)
-	env->sr |= SR_T;
-    else
-	env->sr &= ~SR_T;
-    if (temp < arg)
-	env->sr |= SR_T;
-    return arg;
-}
-
 uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
 {
     uint32_t tmp0, tmp1;

target-sh4/translate.c

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 743d76a..35573be 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -952,7 +952,21 @@
 	tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
 	return;
     case 0x600a:		/* negc Rm,Rn */
-	gen_helper_negc(REG(B11_8), REG(B7_4));
+        {
+	    TCGv t0, t1;
+            t0 = tcg_temp_new();
+            tcg_gen_neg_i32(t0, REG(B7_4));
+            t1 = tcg_temp_new();
+            tcg_gen_andi_i32(t1, cpu_sr, SR_T);
+            tcg_gen_sub_i32(REG(B11_8), t0, t1);
+            tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+            tcg_gen_setcond_i32(TCG_COND_GE, t1, REG(B11_8), t0);
+            tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+            tcg_gen_setcondi_i32(TCG_COND_GE, t1, t0, 0);
+            tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+            tcg_temp_free(t0);
+            tcg_temp_free(t1);
+        }
 	return;
     case 0x6007:		/* not Rm,Rn */
 	tcg_gen_not_i32(REG(B11_8), REG(B7_4));