)]}'
{
  "commit": "b2d7a7c7e4e30fb5341d38deac968de675f9419c",
  "tree": "cb43938ffe2840b746896b1c4f24e62d6de675ad",
  "parents": [
    "3b31b7baff02b357a6c921b26ae953e04d0cfdbb"
  ],
  "author": {
    "name": "Atish Patra",
    "email": "atishp@rivosinc.com",
    "time": "Thu Jul 11 15:31:10 2024 -0700"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Thu Jul 18 12:08:44 2024 +1000"
  },
  "message": "target/riscv: Implement privilege mode filtering for cycle/instret\n\nPrivilege mode filtering can also be emulated for cycle/instret by\ntracking host_ticks/icount during each privilege mode switch. This\npatch implements that for both cycle/instret and mhpmcounters. The\nfirst one requires Smcntrpmf while the other one requires Sscofpmf\nto be enabled.\n\nThe cycle/instret are still computed using host ticks when icount\nis not enabled. Otherwise, they are computed using raw icount which\nis more accurate in icount mode.\n\nCo-Developed-by: Rajnesh Kanwal \u003crkanwal@rivosinc.com\u003e\nSigned-off-by: Rajnesh Kanwal \u003crkanwal@rivosinc.com\u003e\nReviewed-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nAcked-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nSigned-off-by: Atish Patra \u003catishp@rivosinc.com\u003e\nMessage-ID: \u003c20240711-smcntrpmf_v7-v8-7-b7c38ae7b263@rivosinc.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "980e2154cd6b1a90050c8e62223d0ea21b2a39c6",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.h",
      "new_id": "f515ad072bc69211ac8894a87365eb7b888215ef",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "10d3fdaed37687fe07f9ccf0cae83e8c682d2fc9",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu_helper.c",
      "new_id": "395a1d9140615d697408054ed680ad1f9b26a83e",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu_helper.c"
    },
    {
      "type": "modify",
      "old_id": "364583dc038e0340023524e329c904960a3a4030",
      "old_mode": 33188,
      "old_path": "target/riscv/csr.c",
      "new_id": "85d3f0aa3f810159fce06444bb9f115a0bb40be0",
      "new_mode": 33188,
      "new_path": "target/riscv/csr.c"
    },
    {
      "type": "modify",
      "old_id": "0e7d58b8a5c26fd223f45c5d3eef5ebfd0c5265a",
      "old_mode": 33188,
      "old_path": "target/riscv/pmu.c",
      "new_id": "ac648cff8d7c58980cc2346b0aefcd31d203677d",
      "new_mode": 33188,
      "new_path": "target/riscv/pmu.c"
    },
    {
      "type": "modify",
      "old_id": "7c0ad661e05056c482b84c8eb5e9883593af7b5b",
      "old_mode": 33188,
      "old_path": "target/riscv/pmu.h",
      "new_id": "ca40cfeed647bfd47fef31b7e4f94e775ef1b727",
      "new_mode": 33188,
      "new_path": "target/riscv/pmu.h"
    }
  ]
}