)]}'
{
  "commit": "b0daaa172a1cd7e8bc8320bfd6612edbebef157f",
  "tree": "72c8ba3d78b3d137195fb4c9de1ce488ce36e001",
  "parents": [
    "09f89ccc9763a20c0cf9030661af2c04647c1eec"
  ],
  "author": {
    "name": "TANG Tiancheng",
    "email": "lyndra@linux.alibaba.com",
    "time": "Thu Sep 11 17:56:16 2025 +0800"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Fri Oct 03 13:15:14 2025 +1000"
  },
  "message": "target/riscv: Save stimer and vstimer in CPU vmstate\n\nvmstate_riscv_cpu was missing env.stimer and env.vstimer.\nWithout migrating these QEMUTimer fields, active S/VS-mode\ntimer events are lost after snapshot or migration.\n\nAdd VMSTATE_TIMER_PTR() entries to save and restore them.\n\nReviewed-by: LIU Zhiwei \u003czhiwei_liu@linux.alibaba.com\u003e\nReviewed-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nSigned-off-by: TANG Tiancheng \u003clyndra@linux.alibaba.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20250911-timers-v3-4-60508f640050@linux.alibaba.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1600ec44f0b755fdd49fc0df47c2288c9940afe0",
      "old_mode": 33188,
      "old_path": "target/riscv/machine.c",
      "new_id": "51e0567ed30cbab5e791ea904165bc1854709192",
      "new_mode": 33188,
      "new_path": "target/riscv/machine.c"
    }
  ]
}