commit af0b5b7b2a3bd78cd1a01115103c28e2f54d34bc
author Maria Klauchek <m.klauchek@syntacore.com> Mon Sep 02 13:34:33 2024 +0300
committer Alistair Francis <alistair.francis@wdc.com> Wed Oct 02 15:11:51 2024 +1000
tree 1b7042ba79eb74b903627e1654af0853cd0ff739
parent 2d2e3bdc6922553823b7f74fe290805ff49afb32

target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension

FCSR is a part of F extension. Print it to log if FPU option is enabled.

Signed-off-by: Maria Klauchek <m.klauchek@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240902103433.18424-1-m.klauchek@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/cpu.c

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a1ca120..89bc395 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -823,6 +823,12 @@
         }
     }
     if (flags & CPU_DUMP_FPU) {
+        target_ulong val = 0;
+        RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0);
+        if (res == RISCV_EXCP_NONE) {
+            qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                    csr_ops[CSR_FCSR].name, val);
+        }
         for (i = 0; i < 32; i++) {
             qemu_fprintf(f, " %-8s %016" PRIx64,
                          riscv_fpr_regnames[i], env->fpr[i]);