)]}'
{
  "commit": "aeb2bc5950bda70f97c6a7fcbdf1ab2b167d4fa4",
  "tree": "9141d5db29b19b3639809c41b5e84aaea4f218bd",
  "parents": [
    "456a65546f6761aab09275ed7055d113608e3bb2"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Wed Oct 18 16:56:34 2023 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Tue Nov 07 11:06:01 2023 +1000"
  },
  "message": "qapi,risc-v: add query-cpu-model-expansion\n\nThis API is used to inspect the characteristics of a given CPU model. It\nalso allows users to validate a CPU model with a certain configuration,\ne.g. if \"-cpu X,a\u003dtrue,b\u003dfalse\" is a valid setup for a given QEMU\nbinary. We\u0027ll start implementing the first part. The second requires\nmore changes in RISC-V CPU boot flow.\n\nThe implementation is inspired by the existing ARM\nquery-cpu-model-expansion impl in target/arm/arm-qmp-cmds.c. We\u0027ll\ncreate a RISCVCPU object with the required model, fetch its existing\nproperties, add a couple of relevant boolean options (pmp and mmu) and\ndisplay it to users.\n\nHere\u0027s an usage example:\n\n./build/qemu-system-riscv64 -S -M virt -display none \\\n  -qmp  tcp:localhost:1234,server,wait\u003doff\n\n./scripts/qmp/qmp-shell localhost:1234\nWelcome to the QMP low-level shell!\nConnected to QEMU 8.1.50\n\n(QEMU)  query-cpu-model-expansion type\u003dfull model\u003d{\"name\":\"rv64\"}\n{\"return\": {\"model\": {\"name\": \"rv64\", \"props\": {\"zicond\": false, \"x-zvfh\": false, \"mmu\": true, \"x-zvfbfwma\": false, \"x-zvfbfmin\": false, \"xtheadbs\": false, \"xtheadbb\": false, \"xtheadba\": false, \"xtheadmemidx\": false, \"smstateen\": false, \"zfinx\": false, \"Zve64f\": false, \"Zve32f\": false, \"x-zvfhmin\": false, \"xventanacondops\": false, \"xtheadcondmov\": false, \"svpbmt\": false, \"zbs\": true, \"zbc\": true, \"zbb\": true, \"zba\": true, \"zicboz\": true, \"xtheadmac\": false, \"Zfh\": false, \"Zfa\": true, \"zbkx\": false, \"zbkc\": false, \"zbkb\": false, \"Zve64d\": false, \"x-zfbfmin\": false, \"zk\": false, \"x-epmp\": false, \"xtheadmempair\": false, \"zkt\": false, \"zks\": false, \"zkr\": false, \"zkn\": false, \"Zfhmin\": false, \"zksh\": false, \"zknh\": false, \"zkne\": false, \"zknd\": false, \"zhinx\": false, \"Zicsr\": true, \"sscofpmf\": false, \"Zihintntl\": true, \"sstc\": true, \"xtheadcmo\": false, \"x-zvbb\": false, \"zksed\": false, \"x-zvkned\": false, \"xtheadsync\": false, \"x-zvkg\": false, \"zhinxmin\": false, \"svadu\": true, \"xtheadfmv\": false, \"x-zvksed\": false, \"svnapot\": false, \"pmp\": true, \"x-zvknhb\": false, \"x-zvknha\": false, \"xtheadfmemidx\": false, \"x-zvksh\": false, \"zdinx\": false, \"zicbom\": true, \"Zihintpause\": true, \"svinval\": false, \"zcf\": false, \"zce\": false, \"zcd\": false, \"zcb\": false, \"zca\": false, \"x-ssaia\": false, \"x-smaia\": false, \"zmmul\": false, \"x-zvbc\": false, \"Zifencei\": true, \"zcmt\": false, \"zcmp\": false, \"Zawrs\": true}}}}\n\nSigned-off-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20231018195638.211151-3-dbarboza@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c8d7d9868d03ce1c5dc48e2552ba97479d394b53",
      "old_mode": 33188,
      "old_path": "qapi/machine-target.json",
      "new_id": "7b7149f81c64bf157cd7762510453ba10f0fa8ff",
      "new_mode": 33188,
      "new_path": "qapi/machine-target.json"
    },
    {
      "type": "modify",
      "old_id": "5ecff1afb37bb65926a7f4084770176f8cc4c9f8",
      "old_mode": 33188,
      "old_path": "target/riscv/riscv-qmp-cmds.c",
      "new_id": "2170562e3a47332d592854cb3b97d0a3f418e12a",
      "new_mode": 33188,
      "new_path": "target/riscv/riscv-qmp-cmds.c"
    }
  ]
}