tree a1e979f97c5d2d0ad72c7fcba85afe21e1eb0dfc
parent 1c5d07909aea7657c7c6b24223460150526369ba
author Peter Crosthwaite <peter.crosthwaite@xilinx.com> 1362075795 +0000
committer Peter Maydell <peter.maydell@linaro.org> 1362077364 +0000

cadence_gem: fix interrupt events

Bits in the ISR were continually mirroring their corresponding TX/RX SR bits.
This is incorrect. The ISR bits are only ever set at the time their
corresponding event occurs.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: cedfb6d108318846480b416a6041023ea5a353d6.1360901435.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>