commit | ad153f153da08f5e08bc8e433c0070af53e34e0a | [log] [tgz] |
---|---|---|
author | Aurelien Jarno <aurelien@aurel32.net> | Tue Jan 01 18:02:23 2013 +0100 |
committer | Aurelien Jarno <aurelien@aurel32.net> | Thu Jan 31 23:29:36 2013 +0100 |
tree | ed063d1f4b6903aeb2ac7961392fb3e138626331 | |
parent | d75c135e6b6255787dfc01ce997862d820ed1d36 [diff] |
target-mips: generate a reserved instruction exception on CPU without DSP On CPU without DSP ASE support, a reserved instruction exception (instead of a DSP ASE sate disabled) should be generated. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>