xilinx_timer: changed nr_timers to one_timer_only
The configurable property for this IP in the Xilinx tools is a boolean switch
"one-timer-only" that flicks this timer from being dual channel to single.
Updated QEMU to work the same way for better match with the IP core and its TRM.
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index 7d83c21..2cf6882 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -106,7 +106,7 @@
sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]);
/* 2 timers at irq 2 @ 62 Mhz. */
- xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
+ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000);
xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);
microblaze_load_kernel(cpu, ddr_base, ram_size,
