tree fbdbb86dde6ea204fd71839cbf9fc48ee1dfc467
parent 21915d16c6fbe857773cc9e10badb3e29cd7194a
author Daniel Henrique Barboza <dbarboza@ventanamicro.com> 1702904000 -0300
committer Alistair Francis <alistair.francis@wdc.com> 1704876467 +1000

target/riscv/tcg: add riscv_cpu_write_misa_bit()

We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.

Create a helper to avoid code repetition.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231218125334.37184-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>