Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index ebd5b29..824ff0a 100644
--- a/hw/a9mpcore.c
+++ b/hw/a9mpcore.c
@@ -26,7 +26,7 @@
uint32_t num_irq;
} a9mp_priv_state;
-static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t a9_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;
@@ -57,7 +57,7 @@
}
}
-static void a9_scu_write(void *opaque, target_phys_addr_t offset,
+static void a9_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;
diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
index 8079a46..7e7b1d2 100644
--- a/hw/alpha_pci.c
+++ b/hw/alpha_pci.c
@@ -15,7 +15,7 @@
/* PCI IO reads/writes, to byte-word addressable memory. */
/* ??? Doesn't handle multiple PCI busses. */
-static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size)
{
switch (size) {
case 1:
@@ -28,7 +28,7 @@
abort();
}
-static void bw_io_write(void *opaque, target_phys_addr_t addr,
+static void bw_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
switch (size) {
@@ -57,14 +57,14 @@
};
/* PCI config space reads/writes, to byte-word addressable memory. */
-static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIBus *b = opaque;
return pci_data_read(b, addr, size);
}
-static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
+static void bw_conf1_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBus *b = opaque;
@@ -83,12 +83,12 @@
/* PCI/EISA Interrupt Acknowledge Cycle. */
-static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
{
return pic_read_irq(isa_pic);
}
-static void special_write(void *opaque, target_phys_addr_t addr,
+static void special_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
qemu_log("pci: special write cycle");
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index b7cf4e2..9b16d96 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -70,7 +70,7 @@
}
}
-static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
{
CPUAlphaState *env = cpu_single_env;
TyphoonState *s = opaque;
@@ -203,13 +203,13 @@
return ret;
}
-static uint64_t dchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
return 0;
}
-static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
{
TyphoonState *s = opaque;
uint64_t ret = 0;
@@ -306,7 +306,7 @@
return ret;
}
-static void cchip_write(void *opaque, target_phys_addr_t addr,
+static void cchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
@@ -463,13 +463,13 @@
}
}
-static void dchip_write(void *opaque, target_phys_addr_t addr,
+static void dchip_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
}
-static void pchip_write(void *opaque, target_phys_addr_t addr,
+static void pchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
diff --git a/hw/an5206.c b/hw/an5206.c
index 042c5fc..d887c0e 100644
--- a/hw/an5206.c
+++ b/hw/an5206.c
@@ -27,7 +27,7 @@
CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index c28411a..054814f 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -87,7 +87,7 @@
static void pci_apb_set_irq(void *opaque, int irq_num, int level);
-static void apb_config_writel (void *opaque, target_phys_addr_t addr,
+static void apb_config_writel (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@@ -152,7 +152,7 @@
}
static uint64_t apb_config_readl (void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
@@ -212,7 +212,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
+static void apb_pci_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@@ -222,7 +222,7 @@
pci_data_write(s->bus, addr, val, size);
}
-static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t ret;
@@ -234,25 +234,25 @@
return ret;
}
-static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowriteb (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritew (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}
-static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritel (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}
-static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)
{
uint32_t val;
@@ -260,7 +260,7 @@
return val;
}
-static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)
{
uint32_t val;
@@ -268,7 +268,7 @@
return val;
}
-static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)
{
uint32_t val;
@@ -351,8 +351,8 @@
return 0;
}
-PCIBus *pci_apb_init(target_phys_addr_t special_base,
- target_phys_addr_t mem_base,
+PCIBus *pci_apb_init(hwaddr special_base,
+ hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
qemu_irq **pbm_irqs)
{
diff --git a/hw/apb_pci.h b/hw/apb_pci.h
index 55f7c4c..736db61 100644
--- a/hw/apb_pci.h
+++ b/hw/apb_pci.h
@@ -3,8 +3,8 @@
#include "qemu-common.h"
-PCIBus *pci_apb_init(target_phys_addr_t special_base,
- target_phys_addr_t mem_base,
+PCIBus *pci_apb_init(hwaddr special_base,
+ hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
qemu_irq **pbm_irqs);
#endif
diff --git a/hw/apic.c b/hw/apic.c
index 385555e..49f0015 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -630,25 +630,25 @@
apic_timer_update(s, s->next_time);
}
-static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
{
return 0;
}
-static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
{
return 0;
}
-static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
{
}
-static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
{
}
-static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
{
DeviceState *d;
APICCommonState *s;
@@ -732,7 +732,7 @@
return val;
}
-static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
+static void apic_send_msi(hwaddr addr, uint32_t data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
@@ -743,7 +743,7 @@
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
}
-static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
{
DeviceState *d;
APICCommonState *s;
diff --git a/hw/apic_common.c b/hw/apic_common.c
index 371f95d..d68116d 100644
--- a/hw/apic_common.c
+++ b/hw/apic_common.c
@@ -89,7 +89,7 @@
}
}
-void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr)
+void apic_enable_vapic(DeviceState *d, hwaddr paddr)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
diff --git a/hw/apic_internal.h b/hw/apic_internal.h
index 4d8ff49..30932a3 100644
--- a/hw/apic_internal.h
+++ b/hw/apic_internal.h
@@ -124,7 +124,7 @@
uint32_t vapic_control;
DeviceState *vapic;
- target_phys_addr_t vapic_paddr; /* note: persistence via kvmvapic */
+ hwaddr vapic_paddr; /* note: persistence via kvmvapic */
};
typedef struct VAPICState {
@@ -140,7 +140,7 @@
void apic_report_irq_delivered(int delivered);
bool apic_next_timer(APICCommonState *s, int64_t current_time);
void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
-void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr);
+void apic_enable_vapic(DeviceState *d, hwaddr paddr);
void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
TPRAccess access);
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index bdd8fec..d02f7f0 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -30,15 +30,15 @@
const char *kernel_cmdline;
const char *initrd_filename;
const char *dtb_filename;
- target_phys_addr_t loader_start;
+ hwaddr loader_start;
/* multicore boards that use the default secondary core boot functions
* need to put the address of the secondary boot code, the boot reg,
* and the GIC address in the next 3 values, respectively. boards that
* have their own boot functions can use these values as they want.
*/
- target_phys_addr_t smp_loader_start;
- target_phys_addr_t smp_bootreg_addr;
- target_phys_addr_t gic_cpu_if_addr;
+ hwaddr smp_loader_start;
+ hwaddr smp_bootreg_addr;
+ hwaddr gic_cpu_if_addr;
int nb_cpus;
int board_id;
int (*atag_board)(const struct arm_boot_info *info, void *p);
@@ -56,8 +56,8 @@
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
- target_phys_addr_t initrd_size;
- target_phys_addr_t entry;
+ hwaddr initrd_size;
+ hwaddr entry;
};
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index 1bff3d3..105f158 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -27,7 +27,7 @@
/* Per-CPU private memory mapped IO. */
-static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@@ -48,7 +48,7 @@
}
}
-static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
+static void mpcore_scu_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@@ -89,7 +89,7 @@
* at 0x200, 0x300...
*/
for (i = 0; i < (s->num_cpu + 1); i++) {
- target_phys_addr_t offset = 0x100 + (i * 0x100);
+ hwaddr offset = 0x100 + (i * 0x100);
memory_region_add_subregion(&s->container, offset,
sysbus_mmio_get_region(gicbusdev, i + 1));
}
@@ -98,7 +98,7 @@
*/
for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
- target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
+ hwaddr offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
memory_region_add_subregion(&s->container, offset,
sysbus_mmio_get_region(busdev, i));
}
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index a6e9143..09bf6c5 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -89,8 +89,8 @@
static void set_kernel_args(const struct arm_boot_info *info)
{
int initrd_size = info->initrd_size;
- target_phys_addr_t base = info->loader_start;
- target_phys_addr_t p;
+ hwaddr base = info->loader_start;
+ hwaddr p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
@@ -142,10 +142,10 @@
static void set_kernel_args_old(const struct arm_boot_info *info)
{
- target_phys_addr_t p;
+ hwaddr p;
const char *s;
int initrd_size = info->initrd_size;
- target_phys_addr_t base = info->loader_start;
+ hwaddr base = info->loader_start;
/* see linux/include/asm-arm/setup.h */
p = base + KERNEL_ARGS_ADDR;
@@ -213,7 +213,7 @@
}
}
-static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
+static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
{
#ifdef CONFIG_FDT
uint32_t *mem_reg_property;
@@ -342,7 +342,7 @@
int n;
int is_linux = 0;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
int big_endian;
QemuOpts *machine_opts;
@@ -419,7 +419,7 @@
*/
if (info->dtb_filename) {
/* Place the DTB after the initrd in memory */
- target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
+ hwaddr dtb_start = TARGET_PAGE_ALIGN(info->loader_start
+ INITRD_LOAD_ADDR
+ initrd_size);
if (load_dtb(dtb_start, info)) {
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 56376c0..ce16e83 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -212,7 +212,7 @@
}
}
-static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
{
GICState *s = (GICState *)opaque;
uint32_t res;
@@ -328,7 +328,7 @@
return 0;
}
-static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
@@ -336,7 +336,7 @@
return val;
}
-static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
{
uint32_t val;
val = gic_dist_readw(opaque, offset);
@@ -344,7 +344,7 @@
return val;
}
-static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
GICState *s = (GICState *)opaque;
@@ -490,14 +490,14 @@
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
-static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writew(void *opaque, hwaddr offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
-static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writel(void *opaque, hwaddr offset,
uint32_t value)
{
GICState *s = (GICState *)opaque;
@@ -584,14 +584,14 @@
}
/* Wrappers to read/write the GIC CPU interface for the current CPU */
-static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr,
unsigned size)
{
GICState *s = (GICState *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
}
-static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
+static void gic_thiscpu_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GICState *s = (GICState *)opaque;
@@ -601,7 +601,7 @@
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
* These just decode the opaque pointer into GICState* + cpu id.
*/
-static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr,
unsigned size)
{
GICState **backref = (GICState **)opaque;
@@ -610,7 +610,7 @@
return gic_cpu_read(s, id, addr);
}
-static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
+static void gic_do_cpu_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GICState **backref = (GICState **)opaque;
diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c
index de6a086..8f5921c 100644
--- a/hw/arm_l2x0.c
+++ b/hw/arm_l2x0.c
@@ -51,7 +51,7 @@
};
-static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
+static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t cache_data;
@@ -93,7 +93,7 @@
return 0;
}
-static void l2x0_priv_write(void *opaque, target_phys_addr_t offset,
+static void l2x0_priv_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
l2x0_state *s = (l2x0_state *)opaque;
diff --git a/hw/arm_mptimer.c b/hw/arm_mptimer.c
index fe43cbb..6790832 100644
--- a/hw/arm_mptimer.c
+++ b/hw/arm_mptimer.c
@@ -92,7 +92,7 @@
timerblock_update_irq(tb);
}
-static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
+static uint64_t timerblock_read(void *opaque, hwaddr addr,
unsigned size)
{
timerblock *tb = (timerblock *)opaque;
@@ -120,7 +120,7 @@
}
}
-static void timerblock_write(void *opaque, target_phys_addr_t addr,
+static void timerblock_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
timerblock *tb = (timerblock *)opaque;
@@ -159,7 +159,7 @@
/* Wrapper functions to implement the "read timer/watchdog for
* the current CPU" memory regions.
*/
-static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@@ -167,7 +167,7 @@
return timerblock_read(&s->timerblock[id * 2], addr, size);
}
-static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
+static void arm_thistimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@@ -175,7 +175,7 @@
timerblock_write(&s->timerblock[id * 2], addr, value, size);
}
-static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
+static uint64_t arm_thiswdog_read(void *opaque, hwaddr addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@@ -183,7 +183,7 @@
return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
}
-static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
+static void arm_thiswdog_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index 5f1237b..26318e1 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -92,7 +92,7 @@
}
}
-static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
+static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -189,7 +189,7 @@
}
}
-static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
+static void arm_sysctl_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index e3ecce2..2e13621 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -45,7 +45,7 @@
}
}
-static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t arm_timer_read(void *opaque, hwaddr offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@@ -87,7 +87,7 @@
ptimer_set_limit(s->timer, limit, reload);
}
-static void arm_timer_write(void *opaque, target_phys_addr_t offset,
+static void arm_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@@ -202,7 +202,7 @@
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
+static uint64_t sp804_read(void *opaque, hwaddr offset,
unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -230,7 +230,7 @@
return 0;
}
-static void sp804_write(void *opaque, target_phys_addr_t offset,
+static void sp804_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -291,7 +291,7 @@
arm_timer_state *timer[3];
} icp_pit_state;
-static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_pit_read(void *opaque, hwaddr offset,
unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
@@ -306,7 +306,7 @@
return arm_timer_read(s->timer[n], offset & 0xff);
}
-static void icp_pit_write(void *opaque, target_phys_addr_t offset,
+static void icp_pit_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 9f66667..ce2ec9b 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -25,14 +25,14 @@
}
-static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readb(void *opaque, hwaddr offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
-static void bitband_writeb(void *opaque, target_phys_addr_t offset,
+static void bitband_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
@@ -48,7 +48,7 @@
cpu_physical_memory_write(addr, &v, 1);
}
-static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readw(void *opaque, hwaddr offset)
{
uint32_t addr;
uint16_t mask;
@@ -60,7 +60,7 @@
return (v & mask) != 0;
}
-static void bitband_writew(void *opaque, target_phys_addr_t offset,
+static void bitband_writew(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
@@ -77,7 +77,7 @@
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
-static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readl(void *opaque, hwaddr offset)
{
uint32_t addr;
uint32_t mask;
@@ -89,7 +89,7 @@
return (v & mask) != 0;
}
-static void bitband_writel(void *opaque, target_phys_addr_t offset,
+static void bitband_writel(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index c449e08..35c1aa6 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -392,7 +392,7 @@
}
}
-static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
unsigned size)
{
/* At the moment we only support the ID registers for byte/word access.
@@ -412,7 +412,7 @@
hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
}
-static void nvic_sysreg_write(void *opaque, target_phys_addr_t addr,
+static void nvic_sysreg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
uint32_t offset = addr;
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index 2fd7356..aa1ac9e 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -47,7 +47,7 @@
};
static struct nand_state_t nand_state;
-static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t r;
@@ -62,7 +62,7 @@
}
static void
-nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+nand_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
struct nand_state_t *s = opaque;
@@ -166,7 +166,7 @@
uint32_t regs[0x5c / 4];
} gpio_state;
-static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@@ -195,7 +195,7 @@
D(printf("%s %x=%x\n", __func__, addr, r));
}
-static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
struct gpio_state_t *s = opaque;
diff --git a/hw/bonito.c b/hw/bonito.c
index 6084ac4..0bf6d4a 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -211,12 +211,12 @@
MemoryRegion iomem_ldma;
MemoryRegion iomem_cop;
- target_phys_addr_t bonito_pciio_start;
- target_phys_addr_t bonito_pciio_length;
+ hwaddr bonito_pciio_start;
+ hwaddr bonito_pciio_length;
int bonito_pciio_handle;
- target_phys_addr_t bonito_localio_start;
- target_phys_addr_t bonito_localio_length;
+ hwaddr bonito_localio_start;
+ hwaddr bonito_localio_length;
int bonito_localio_handle;
} PCIBonitoState;
@@ -232,7 +232,7 @@
PCIBonitoState *pci_dev;
};
-static void bonito_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -295,7 +295,7 @@
}
}
-static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_readl(void *opaque, hwaddr addr,
unsigned size)
{
PCIBonitoState *s = opaque;
@@ -322,7 +322,7 @@
},
};
-static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_pciconf_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -332,7 +332,7 @@
d->config_write(d, addr, val, 4);
}
-static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
unsigned size)
{
@@ -355,7 +355,7 @@
},
};
-static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
@@ -366,7 +366,7 @@
return val;
}
-static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_ldma_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -384,7 +384,7 @@
},
};
-static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
@@ -395,7 +395,7 @@
return val;
}
-static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_cop_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -413,7 +413,7 @@
},
};
-static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
@@ -449,7 +449,7 @@
return pciaddr;
}
-static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@@ -475,7 +475,7 @@
pci_set_word(d->config + PCI_STATUS, status);
}
-static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writew(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@@ -503,7 +503,7 @@
pci_set_word(d->config + PCI_STATUS, status);
}
-static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writel(void *opaque, hwaddr addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@@ -531,7 +531,7 @@
pci_set_word(d->config + PCI_STATUS, status);
}
-static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
@@ -557,7 +557,7 @@
return pci_data_read(phb->bus, phb->config_reg, 1);
}
-static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
@@ -585,7 +585,7 @@
return pci_data_read(phb->bus, phb->config_reg, 2);
}
-static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
{
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
index 967f625..0c037a2 100644
--- a/hw/cadence_gem.c
+++ b/hw/cadence_gem.c
@@ -605,7 +605,7 @@
static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
unsigned desc[2];
- target_phys_addr_t packet_desc_addr, last_desc_addr;
+ hwaddr packet_desc_addr, last_desc_addr;
GemState *s;
unsigned rxbufsize, bytes_to_copy;
unsigned rxbuf_offset;
@@ -824,7 +824,7 @@
static void gem_transmit(GemState *s)
{
unsigned desc[2];
- target_phys_addr_t packet_desc_addr;
+ hwaddr packet_desc_addr;
uint8_t tx_packet[2048];
uint8_t *p;
unsigned total_bytes;
@@ -1021,7 +1021,7 @@
* gem_read32:
* Read a GEM register.
*/
-static uint64_t gem_read(void *opaque, target_phys_addr_t offset, unsigned size)
+static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
{
GemState *s;
uint32_t retval;
@@ -1067,7 +1067,7 @@
* gem_write32:
* Write a GEM register.
*/
-static void gem_write(void *opaque, target_phys_addr_t offset, uint64_t val,
+static void gem_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
{
GemState *s = (GemState *)opaque;
diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
index 77b6976..ec78a52 100644
--- a/hw/cadence_ttc.c
+++ b/hw/cadence_ttc.c
@@ -76,7 +76,7 @@
}
static CadenceTimerState *cadence_timer_from_addr(void *opaque,
- target_phys_addr_t offset)
+ hwaddr offset)
{
unsigned int index;
CadenceTTCState *s = (CadenceTTCState *)opaque;
@@ -224,7 +224,7 @@
cadence_timer_run(s);
}
-static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
+static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
{
CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
uint32_t value;
@@ -297,7 +297,7 @@
}
}
-static uint64_t cadence_ttc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t ret = cadence_ttc_read_imp(opaque, offset);
@@ -306,7 +306,7 @@
return ret;
}
-static void cadence_ttc_write(void *opaque, target_phys_addr_t offset,
+static void cadence_ttc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index f8afc4e..a7d0504 100644
--- a/hw/cadence_uart.c
+++ b/hw/cadence_uart.c
@@ -354,7 +354,7 @@
uart_update_status(s);
}
-static void uart_write(void *opaque, target_phys_addr_t offset,
+static void uart_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
UartState *s = (UartState *)opaque;
@@ -397,7 +397,7 @@
}
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t offset,
+static uint64_t uart_read(void *opaque, hwaddr offset,
unsigned size)
{
UartState *s = (UartState *)opaque;
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index a101329..e4af2e9 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1952,7 +1952,7 @@
***************************************/
static uint64_t cirrus_vga_mem_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint32_t size)
{
CirrusVGAState *s = opaque;
@@ -1996,7 +1996,7 @@
}
static void cirrus_vga_mem_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t mem_value,
uint32_t size)
{
@@ -2255,7 +2255,7 @@
*
***************************************/
-static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2284,7 +2284,7 @@
return ret;
}
-static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
+static void cirrus_linear_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2333,7 +2333,7 @@
static uint64_t cirrus_linear_bitblt_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2346,7 +2346,7 @@
}
static void cirrus_linear_bitblt_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t val,
unsigned size)
{
@@ -2640,7 +2640,7 @@
*
***************************************/
-static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2652,7 +2652,7 @@
}
}
-static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
+static void cirrus_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
diff --git a/hw/cris-boot.h b/hw/cris-boot.h
index 0a2c242..5b17d83 100644
--- a/hw/cris-boot.h
+++ b/hw/cris-boot.h
@@ -5,7 +5,7 @@
const char *cmdline;
int image_size;
- target_phys_addr_t entry;
+ hwaddr entry;
};
void cris_load_image(CRISCPU *cpu, struct cris_load_info *li);
diff --git a/hw/cs4231.c b/hw/cs4231.c
index cfec1d9..23570d5 100644
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -55,7 +55,7 @@
s->dregs[25] = CS_VER;
}
-static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cs_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
CSState *s = opaque;
@@ -82,7 +82,7 @@
return ret;
}
-static void cs_mem_write(void *opaque, target_phys_addr_t addr,
+static void cs_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
CSState *s = opaque;
diff --git a/hw/cs4231a.c b/hw/cs4231a.c
index e07b9d6..0257fd8 100644
--- a/hw/cs4231a.c
+++ b/hw/cs4231a.c
@@ -346,7 +346,7 @@
}
}
-static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t cs_read (void *opaque, hwaddr addr, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, ret;
@@ -383,7 +383,7 @@
return ret;
}
-static void cs_write (void *opaque, target_phys_addr_t addr,
+static void cs_write (void *opaque, hwaddr addr,
uint64_t val64, unsigned size)
{
CSState *s = opaque;
diff --git a/hw/cuda.c b/hw/cuda.c
index 233ab66..f1f408b 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -252,7 +252,7 @@
cuda_update_irq(s);
}
-static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readb(void *opaque, hwaddr addr)
{
CUDAState *s = opaque;
uint32_t val;
@@ -325,7 +325,7 @@
return val;
}
-static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
{
CUDAState *s = opaque;
@@ -616,20 +616,20 @@
}
}
-static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void cuda_writew (void *opaque, hwaddr addr, uint32_t value)
{
}
-static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void cuda_writel (void *opaque, hwaddr addr, uint32_t value)
{
}
-static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readw (void *opaque, hwaddr addr)
{
return 0;
}
-static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readl (void *opaque, hwaddr addr)
{
return 0;
}
diff --git a/hw/dma.c b/hw/dma.c
index 0a9322d..d6aeac2 100644
--- a/hw/dma.c
+++ b/hw/dma.c
@@ -411,7 +411,7 @@
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
@@ -433,7 +433,7 @@
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
diff --git a/hw/dp8393x.c b/hw/dp8393x.c
index 4fa6ecc..3f6386e 100644
--- a/hw/dp8393x.c
+++ b/hw/dp8393x.c
@@ -168,7 +168,7 @@
int loopback_packet;
/* Memory access */
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
@@ -603,7 +603,7 @@
dp8393x_update_irq(s);
}
-static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readw(void *opaque, hwaddr addr)
{
dp8393xState *s = opaque;
int reg;
@@ -616,13 +616,13 @@
return read_register(s, reg);
}
-static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readb(void *opaque, hwaddr addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readl(void *opaque, hwaddr addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
@@ -630,7 +630,7 @@
return v;
}
-static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writew(void *opaque, hwaddr addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
@@ -644,7 +644,7 @@
write_register(s, reg, (uint16_t)val);
}
-static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
@@ -659,7 +659,7 @@
dp8393x_writew(opaque, addr & ~0x1, val);
}
-static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writel(void *opaque, hwaddr addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@@ -879,10 +879,10 @@
.cleanup = nic_cleanup,
};
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
diff --git a/hw/ds1225y.c b/hw/ds1225y.c
index 2cd355b..4b3f69b 100644
--- a/hw/ds1225y.c
+++ b/hw/ds1225y.c
@@ -34,7 +34,7 @@
uint8_t *contents;
} NvRamState;
-static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
{
NvRamState *s = opaque;
uint32_t val;
@@ -44,7 +44,7 @@
return val;
}
-static void nvram_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
NvRamState *s = opaque;
diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c
index f436a0c..20f790b 100644
--- a/hw/dummy_m68k.c
+++ b/hw/dummy_m68k.c
@@ -26,7 +26,7 @@
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
if (!cpu_model)
cpu_model = "cfv4e";
diff --git a/hw/e1000.c b/hw/e1000.c
index 63fee10..e4f1ffe 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1011,7 +1011,7 @@
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
-e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
E1000State *s = opaque;
@@ -1028,7 +1028,7 @@
}
static uint64_t
-e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
+e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@@ -1051,7 +1051,7 @@
},
};
-static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t e1000_io_read(void *opaque, hwaddr addr,
unsigned size)
{
E1000State *s = opaque;
@@ -1060,7 +1060,7 @@
return 0;
}
-static void e1000_io_write(void *opaque, target_phys_addr_t addr,
+static void e1000_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
E1000State *s = opaque;
diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c
index fe1cd90..000bd08 100644
--- a/hw/eccmemctl.c
+++ b/hw/eccmemctl.c
@@ -129,7 +129,7 @@
uint32_t version;
} ECCState;
-static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
ECCState *s = opaque;
@@ -172,7 +172,7 @@
}
}
-static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
ECCState *s = opaque;
@@ -229,7 +229,7 @@
},
};
-static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
+static void ecc_diag_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
ECCState *s = opaque;
@@ -238,7 +238,7 @@
s->diag[addr & ECC_DIAG_MASK] = val;
}
-static uint64_t ecc_diag_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
ECCState *s = opaque;
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 5b23116..a189474 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1578,7 +1578,7 @@
}
}
-static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
+static uint64_t eepro100_read(void *opaque, hwaddr addr,
unsigned size)
{
EEPRO100State *s = opaque;
@@ -1591,7 +1591,7 @@
}
}
-static void eepro100_write(void *opaque, target_phys_addr_t addr,
+static void eepro100_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
EEPRO100State *s = opaque;
diff --git a/hw/elf_ops.h b/hw/elf_ops.h
index 731a983..531a425 100644
--- a/hw/elf_ops.h
+++ b/hw/elf_ops.h
@@ -62,7 +62,7 @@
static int glue(symfind, SZ)(const void *s0, const void *s1)
{
- target_phys_addr_t addr = *(target_phys_addr_t *)s0;
+ hwaddr addr = *(hwaddr *)s0;
struct elf_sym *sym = (struct elf_sym *)s1;
int result = 0;
if (addr < sym->st_value) {
@@ -74,7 +74,7 @@
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
- target_phys_addr_t orig_addr)
+ hwaddr orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym *sym;
diff --git a/hw/empty_slot.c b/hw/empty_slot.c
index 099c85e..23978eb 100644
--- a/hw/empty_slot.c
+++ b/hw/empty_slot.c
@@ -28,14 +28,14 @@
uint64_t size;
} EmptySlot;
-static uint64_t empty_slot_read(void *opaque, target_phys_addr_t addr,
+static uint64_t empty_slot_read(void *opaque, hwaddr addr,
unsigned size)
{
DPRINTF("read from " TARGET_FMT_plx "\n", addr);
return 0;
}
-static void empty_slot_write(void *opaque, target_phys_addr_t addr,
+static void empty_slot_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
@@ -47,7 +47,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
+void empty_slot_init(hwaddr addr, uint64_t slot_size)
{
if (slot_size > 0) {
/* Only empty slots larger than 0 byte need handling. */
diff --git a/hw/empty_slot.h b/hw/empty_slot.h
index 78dc91d..4e9e460 100644
--- a/hw/empty_slot.h
+++ b/hw/empty_slot.h
@@ -1,2 +1,2 @@
/* empty_slot.c */
-void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size);
+void empty_slot_init(hwaddr addr, uint64_t slot_size);
diff --git a/hw/escc.c b/hw/escc.c
index e1f5e73..a356613 100644
--- a/hw/escc.c
+++ b/hw/escc.c
@@ -463,7 +463,7 @@
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
-static void escc_mem_write(void *opaque, target_phys_addr_t addr,
+static void escc_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SerialState *serial = opaque;
@@ -565,7 +565,7 @@
}
}
-static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t escc_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SerialState *serial = opaque;
@@ -683,7 +683,7 @@
}
};
-MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
@@ -846,7 +846,7 @@
put_queue(s, 0);
}
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;
diff --git a/hw/escc.h b/hw/escc.h
index d1da46f..def2894 100644
--- a/hw/escc.h
+++ b/hw/escc.h
@@ -1,8 +1,8 @@
/* escc.c */
#define ESCC_SIZE 4
-MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
int disabled, int clock, int it_shift);
diff --git a/hw/esp-pci.c b/hw/esp-pci.c
index 170e007..d9a8e59 100644
--- a/hw/esp-pci.c
+++ b/hw/esp-pci.c
@@ -159,7 +159,7 @@
return val;
}
-static void esp_pci_io_write(void *opaque, target_phys_addr_t addr,
+static void esp_pci_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
PCIESPState *pci = opaque;
@@ -202,7 +202,7 @@
}
}
-static uint64_t esp_pci_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
PCIESPState *pci = opaque;
diff --git a/hw/esp.c b/hw/esp.c
index 84a4e74..6d01624 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -550,7 +550,7 @@
s->wregs[saddr] = val;
}
-static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
+static bool esp_mem_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 4);
@@ -585,7 +585,7 @@
ESPState esp;
} SysBusESPState;
-static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr,
+static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
SysBusESPState *sysbus = opaque;
@@ -595,7 +595,7 @@
esp_reg_write(&sysbus->esp, saddr, val);
}
-static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
unsigned int size)
{
SysBusESPState *sysbus = opaque;
@@ -612,7 +612,7 @@
.valid.accepts = esp_mem_accepts,
};
-void esp_init(target_phys_addr_t espaddr, int it_shift,
+void esp_init(hwaddr espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
diff --git a/hw/esp.h b/hw/esp.h
index fa855e2..f15cc7b 100644
--- a/hw/esp.h
+++ b/hw/esp.h
@@ -6,7 +6,7 @@
/* esp.c */
#define ESP_MAX_DEVS 7
typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
-void esp_init(target_phys_addr_t espaddr, int it_shift,
+void esp_init(hwaddr espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
diff --git a/hw/etraxfs.h b/hw/etraxfs.h
index c62f94b..725bb9e 100644
--- a/hw/etraxfs.h
+++ b/hw/etraxfs.h
@@ -29,7 +29,7 @@
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
-etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr,
+etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
void *dma_out, void *dma_in)
{
DeviceState *dev;
diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c
index 332525c..49221ab 100644
--- a/hw/etraxfs_dma.c
+++ b/hw/etraxfs_dma.c
@@ -212,7 +212,7 @@
&& ctrl->channels[c].client;
}
-static inline int fs_channel(target_phys_addr_t addr)
+static inline int fs_channel(hwaddr addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
@@ -221,7 +221,7 @@
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@@ -253,7 +253,7 @@
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@@ -270,7 +270,7 @@
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -284,7 +284,7 @@
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -296,7 +296,7 @@
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -573,14 +573,14 @@
return 0;
}
-static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
+static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint64_t
-dma_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+dma_read(void *opaque, hwaddr addr, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@@ -612,7 +612,7 @@
}
static void
-dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
+dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
@@ -627,7 +627,7 @@
}
static void
-dma_write(void *opaque, target_phys_addr_t addr,
+dma_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
@@ -762,7 +762,7 @@
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
-void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
+void *etraxfs_dmac_init(hwaddr base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;
diff --git a/hw/etraxfs_dma.h b/hw/etraxfs_dma.h
index 021c52a..3fef80f 100644
--- a/hw/etraxfs_dma.h
+++ b/hw/etraxfs_dma.h
@@ -20,7 +20,7 @@
} client;
};
-void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
+void *etraxfs_dmac_init(hwaddr base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,
diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c
index b124f5b..3d42426 100644
--- a/hw/etraxfs_eth.c
+++ b/hw/etraxfs_eth.c
@@ -374,7 +374,7 @@
}
static uint64_t
-eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+eth_read(void *opaque, hwaddr addr, unsigned int size)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
@@ -418,7 +418,7 @@
}
static void
-eth_write(void *opaque, target_phys_addr_t addr,
+eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct fs_eth *eth = opaque;
diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
index dc27f88..62a62a3 100644
--- a/hw/etraxfs_pic.c
+++ b/hw/etraxfs_pic.c
@@ -79,7 +79,7 @@
}
static uint64_t
-pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+pic_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
@@ -89,7 +89,7 @@
return rval;
}
-static void pic_write(void *opaque, target_phys_addr_t addr,
+static void pic_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
struct etrax_pic *fs = opaque;
diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
index 5f16b17..ee0d72b 100644
--- a/hw/etraxfs_ser.c
+++ b/hw/etraxfs_ser.c
@@ -75,7 +75,7 @@
}
static uint64_t
-ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+ser_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_serial *s = opaque;
D(CPUCRISState *env = s->env);
@@ -110,7 +110,7 @@
}
static void
-ser_write(void *opaque, target_phys_addr_t addr,
+ser_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_serial *s = opaque;
diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c
index 9076a49..f5601dc 100644
--- a/hw/etraxfs_timer.c
+++ b/hw/etraxfs_timer.c
@@ -75,7 +75,7 @@
};
static uint64_t
-timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+timer_read(void *opaque, hwaddr addr, unsigned int size)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
@@ -242,7 +242,7 @@
}
static void
-timer_write(void *opaque, target_phys_addr_t addr,
+timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_timer *t = opaque;
diff --git a/hw/exynos4210.h b/hw/exynos4210.h
index a43ba3a..777f0f5 100644
--- a/hw/exynos4210.h
+++ b/hw/exynos4210.h
@@ -128,7 +128,7 @@
/*
* exynos4210 UART
*/
-DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
+DeviceState *exynos4210_uart_create(hwaddr addr,
int fifo_size,
int channel,
CharDriverState *chr,
diff --git a/hw/exynos4210_combiner.c b/hw/exynos4210_combiner.c
index 60b33c7..84d36ed 100644
--- a/hw/exynos4210_combiner.c
+++ b/hw/exynos4210_combiner.c
@@ -174,7 +174,7 @@
}
static uint64_t
-exynos4210_combiner_read(void *opaque, target_phys_addr_t offset, unsigned size)
+exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
{
struct Exynos4210CombinerState *s =
(struct Exynos4210CombinerState *)opaque;
@@ -266,7 +266,7 @@
}
}
-static void exynos4210_combiner_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_combiner_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
struct Exynos4210CombinerState *s =
diff --git a/hw/exynos4210_fimd.c b/hw/exynos4210_fimd.c
index 3313f00..7cb2c31 100644
--- a/hw/exynos4210_fimd.c
+++ b/hw/exynos4210_fimd.c
@@ -290,7 +290,7 @@
uint16_t virtpage_offsize; /* VIDWADD2 register */
MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
- target_phys_addr_t fb_len; /* Framebuffer length */
+ hwaddr fb_len; /* Framebuffer length */
};
typedef struct {
@@ -1110,7 +1110,7 @@
static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
{
Exynos4210fimdWindow *w = &s->window[win];
- target_phys_addr_t fb_start_addr, fb_mapped_len;
+ hwaddr fb_start_addr, fb_mapped_len;
if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
@@ -1243,7 +1243,7 @@
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
Exynos4210fimdWindow *w;
int i, line;
- target_phys_addr_t fb_line_addr, inc_size;
+ hwaddr fb_line_addr, inc_size;
int scrn_height;
int first_line = -1, last_line = -1, scrn_width;
bool blend = false;
@@ -1348,7 +1348,7 @@
s->hueoffset = 0x01800080;
}
-static void exynos4210_fimd_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_fimd_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
@@ -1649,7 +1649,7 @@
}
}
-static uint64_t exynos4210_fimd_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
diff --git a/hw/exynos4210_i2c.c b/hw/exynos4210_i2c.c
index 3f72a5c..1e11d9b 100644
--- a/hw/exynos4210_i2c.c
+++ b/hw/exynos4210_i2c.c
@@ -129,7 +129,7 @@
exynos4210_i2c_raise_interrupt(s);
}
-static uint64_t exynos4210_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
@@ -168,7 +168,7 @@
return value;
}
-static void exynos4210_i2c_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
diff --git a/hw/exynos4210_mct.c b/hw/exynos4210_mct.c
index 6f94ce2..e79cd6a 100644
--- a/hw/exynos4210_mct.c
+++ b/hw/exynos4210_mct.c
@@ -985,7 +985,7 @@
}
/* Multi Core Timer read */
-static uint64_t exynos4210_mct_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
@@ -1098,7 +1098,7 @@
}
/* MCT write */
-static void exynos4210_mct_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_mct_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c
index c12d750..a22b8f1 100644
--- a/hw/exynos4210_pmu.c
+++ b/hw/exynos4210_pmu.c
@@ -392,7 +392,7 @@
uint32_t reg[PMU_NUM_OF_REGISTERS];
} Exynos4210PmuState;
-static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
@@ -411,7 +411,7 @@
return 0;
}
-static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_pmu_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
diff --git a/hw/exynos4210_pwm.c b/hw/exynos4210_pwm.c
index 0c22828..5e2872f 100644
--- a/hw/exynos4210_pwm.c
+++ b/hw/exynos4210_pwm.c
@@ -208,7 +208,7 @@
/*
* PWM Read
*/
-static uint64_t exynos4210_pwm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
@@ -259,7 +259,7 @@
/*
* PWM Write
*/
-static void exynos4210_pwm_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_pwm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
diff --git a/hw/exynos4210_rtc.c b/hw/exynos4210_rtc.c
index 42a4ddc..c4fbd49 100644
--- a/hw/exynos4210_rtc.c
+++ b/hw/exynos4210_rtc.c
@@ -299,7 +299,7 @@
/*
* RTC Read
*/
-static uint64_t exynos4210_rtc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t value = 0;
@@ -376,7 +376,7 @@
/*
* RTC Write
*/
-static void exynos4210_rtc_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_rtc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
diff --git a/hw/exynos4210_uart.c b/hw/exynos4210_uart.c
index ccc47804..20dcd9f 100644
--- a/hw/exynos4210_uart.c
+++ b/hw/exynos4210_uart.c
@@ -96,7 +96,7 @@
typedef struct Exynos4210UartReg {
const char *name; /* the only reason is the debug output */
- target_phys_addr_t offset;
+ hwaddr offset;
uint32_t reset_value;
} Exynos4210UartReg;
@@ -184,7 +184,7 @@
#if DEBUG_UART
/* Used only for debugging inside PRINT_DEBUG_... macros */
-static const char *exynos4210_uart_regname(target_phys_addr_t offset)
+static const char *exynos4210_uart_regname(hwaddr offset)
{
int regs_number = sizeof(exynos4210_uart_regs) / sizeof(Exynos4210UartReg);
@@ -348,7 +348,7 @@
s->channel, speed, parity, data_bits, stop_bits);
}
-static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset,
+static void exynos4210_uart_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
@@ -423,7 +423,7 @@
break;
}
}
-static uint64_t exynos4210_uart_read(void *opaque, target_phys_addr_t offset,
+static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
@@ -581,7 +581,7 @@
}
};
-DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
+DeviceState *exynos4210_uart_create(hwaddr addr,
int fifo_size,
int channel,
CharDriverState *chr,
@@ -617,7 +617,7 @@
bus = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
sysbus_connect_irq(bus, 0, irq);
diff --git a/hw/fdc.c b/hw/fdc.c
index 25a49e3..bf8c1d9 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -626,13 +626,13 @@
}
}
-static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
+static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
unsigned ize)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
-static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
+static void fdctrl_write_mem (void *opaque, hwaddr reg,
uint64_t value, unsigned size)
{
fdctrl_write(opaque, (uint32_t)reg, value);
@@ -2032,7 +2032,7 @@
}
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds)
+ hwaddr mmio_base, DriveInfo **fds)
{
FDCtrl *fdctrl;
DeviceState *dev;
@@ -2053,7 +2053,7 @@
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
}
-void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;
diff --git a/hw/fdc.h b/hw/fdc.h
index b5c9f31..a8f6f7c 100644
--- a/hw/fdc.h
+++ b/hw/fdc.h
@@ -15,8 +15,8 @@
ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds);
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds);
-void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+ hwaddr mmio_base, DriveInfo **fds);
+void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc);
FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i);
diff --git a/hw/flash.h b/hw/flash.h
index 9c9e526..d790f3c 100644
--- a/hw/flash.h
+++ b/hw/flash.h
@@ -5,18 +5,18 @@
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
-pflash_t *pflash_cfi01_register(target_phys_addr_t base,
+pflash_t *pflash_cfi01_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be);
/* pflash_cfi02.c */
-pflash_t *pflash_cfi02_register(target_phys_addr_t base,
+pflash_t *pflash_cfi02_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
diff --git a/hw/framebuffer.c b/hw/framebuffer.c
index 27fa6f5..fa0f786 100644
--- a/hw/framebuffer.c
+++ b/hw/framebuffer.c
@@ -26,7 +26,7 @@
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
- target_phys_addr_t base,
+ hwaddr base,
int cols, /* Width in pixels. */
int rows, /* Height in pixels. */
int src_width, /* Length of source line, in bytes. */
@@ -38,7 +38,7 @@
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
- target_phys_addr_t src_len;
+ hwaddr src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
diff --git a/hw/framebuffer.h b/hw/framebuffer.h
index 527a6b8..46e375b 100644
--- a/hw/framebuffer.h
+++ b/hw/framebuffer.h
@@ -10,7 +10,7 @@
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
- target_phys_addr_t base,
+ hwaddr base,
int cols,
int rows,
int src_width,
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index dcde1a9..2b92cda 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -258,37 +258,37 @@
return ret;
}
-static uint64_t fw_cfg_data_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t fw_cfg_data_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_data_mem_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_write(opaque, (uint8_t)value);
}
-static void fw_cfg_ctl_mem_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_select(opaque, (uint16_t)value);
}
-static bool fw_cfg_ctl_mem_valid(void *opaque, target_phys_addr_t addr,
+static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write && size == 2;
}
-static uint64_t fw_cfg_comb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_comb_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
@@ -301,7 +301,7 @@
}
}
-static bool fw_cfg_comb_valid(void *opaque, target_phys_addr_t addr,
+static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 2);
@@ -494,7 +494,7 @@
}
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
+ hwaddr ctl_addr, hwaddr data_addr)
{
DeviceState *dev;
SysBusDevice *d;
diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
index 856bf91..619a394 100644
--- a/hw/fw_cfg.h
+++ b/hw/fw_cfg.h
@@ -63,7 +63,7 @@
int fw_cfg_add_file(FWCfgState *s, const char *filename, uint8_t *data,
uint32_t len);
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
+ hwaddr crl_addr, hwaddr data_addr);
#endif /* NO_QEMU_PROTOS */
diff --git a/hw/g364fb.c b/hw/g364fb.c
index 059e622..f7b4bf5 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -362,7 +362,7 @@
/* called for accesses to io ports */
static uint64_t g364fb_ctrl_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned int size)
{
G364State *s = opaque;
@@ -424,7 +424,7 @@
}
static void g364fb_ctrl_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t val,
unsigned int size)
{
diff --git a/hw/grlib.h b/hw/grlib.h
index e1c4137..35c22f5 100644
--- a/hw/grlib.h
+++ b/hw/grlib.h
@@ -41,7 +41,7 @@
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
-DeviceState *grlib_irqmp_create(target_phys_addr_t base,
+DeviceState *grlib_irqmp_create(hwaddr base,
CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
@@ -73,7 +73,7 @@
/* GPTimer */
static inline
-DeviceState *grlib_gptimer_create(target_phys_addr_t base,
+DeviceState *grlib_gptimer_create(hwaddr base,
uint32_t nr_timers,
uint32_t freq,
qemu_irq *cpu_irqs,
@@ -103,7 +103,7 @@
/* APB UART */
static inline
-DeviceState *grlib_apbuart_create(target_phys_addr_t base,
+DeviceState *grlib_apbuart_create(hwaddr base,
CharDriverState *serial,
qemu_irq irq)
{
diff --git a/hw/grlib_apbuart.c b/hw/grlib_apbuart.c
index 73fc989..0865764 100644
--- a/hw/grlib_apbuart.c
+++ b/hw/grlib_apbuart.c
@@ -151,7 +151,7 @@
}
-static uint64_t grlib_apbuart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
unsigned size)
{
UART *uart = opaque;
@@ -181,7 +181,7 @@
}
}
-static void grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
+static void grlib_apbuart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
UART *uart = opaque;
diff --git a/hw/grlib_gptimer.c b/hw/grlib_gptimer.c
index 41770a9..2fdccfb 100644
--- a/hw/grlib_gptimer.c
+++ b/hw/grlib_gptimer.c
@@ -155,11 +155,11 @@
}
}
-static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
unsigned size)
{
GPTimerUnit *unit = opaque;
- target_phys_addr_t timer_addr;
+ hwaddr timer_addr;
int id;
uint32_t value = 0;
@@ -214,11 +214,11 @@
return 0;
}
-static void grlib_gptimer_write(void *opaque, target_phys_addr_t addr,
+static void grlib_gptimer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
GPTimerUnit *unit = opaque;
- target_phys_addr_t timer_addr;
+ hwaddr timer_addr;
int id;
addr &= 0xff;
diff --git a/hw/grlib_irqmp.c b/hw/grlib_irqmp.c
index 0f6e65c..23a6a02 100644
--- a/hw/grlib_irqmp.c
+++ b/hw/grlib_irqmp.c
@@ -162,7 +162,7 @@
}
}
-static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
unsigned size)
{
IRQMP *irqmp = opaque;
@@ -226,7 +226,7 @@
return 0;
}
-static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
+static void grlib_irqmp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
IRQMP *irqmp = opaque;
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index e95e664..95d491d 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -225,8 +225,8 @@
#define GT_PCI1_SERR1MASK (0xca8 >> 2)
#define PCI_MAPPING_ENTRY(regname) \
- target_phys_addr_t regname ##_start; \
- target_phys_addr_t regname ##_length; \
+ hwaddr regname ##_start; \
+ hwaddr regname ##_length; \
MemoryRegion regname ##_mem
#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
@@ -245,11 +245,11 @@
/* Adjust range to avoid touching space which isn't mappable via PCI */
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
0x1fc00000 - 0x1fd00000 */
-static void check_reserved_space (target_phys_addr_t *start,
- target_phys_addr_t *length)
+static void check_reserved_space (hwaddr *start,
+ hwaddr *length)
{
- target_phys_addr_t begin = *start;
- target_phys_addr_t end = *start + *length;
+ hwaddr begin = *start;
+ hwaddr end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL)
end = 0x1e000000LL;
@@ -271,8 +271,8 @@
static void gt64120_isd_mapping(GT64120State *s)
{
- target_phys_addr_t start = s->regs[GT_ISD] << 21;
- target_phys_addr_t length = 0x1000;
+ hwaddr start = s->regs[GT_ISD] << 21;
+ hwaddr length = 0x1000;
if (s->ISD_length) {
memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
@@ -311,7 +311,7 @@
}
}
-static void gt64120_writel (void *opaque, target_phys_addr_t addr,
+static void gt64120_writel (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
GT64120State *s = opaque;
@@ -594,7 +594,7 @@
}
static uint64_t gt64120_readl (void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index 16f48d1..b9ec8e7 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -63,7 +63,7 @@
}
}
-static void pic_write(void *opaque, target_phys_addr_t addr,
+static void pic_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
HeathrowPICS *s = opaque;
@@ -91,7 +91,7 @@
}
}
-static uint64_t pic_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pic_read(void *opaque, hwaddr addr,
unsigned size)
{
HeathrowPICS *s = opaque;
diff --git a/hw/highbank.c b/hw/highbank.c
index 15036b6..afbb005 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -79,7 +79,7 @@
}
#define NUM_REGS 0x200
-static void hb_regs_write(void *opaque, target_phys_addr_t offset,
+static void hb_regs_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
uint32_t *regs = opaque;
@@ -95,7 +95,7 @@
regs[offset/4] = value;
}
-static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
+static uint64_t hb_regs_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t *regs = opaque;
diff --git a/hw/hpet.c b/hw/hpet.c
index fd3ddca..50ac067 100644
--- a/hw/hpet.c
+++ b/hw/hpet.c
@@ -370,20 +370,20 @@
}
#ifdef HPET_DEBUG
-static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
{
printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
return 0;
}
-static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
{
printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
return 0;
}
#endif
-static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
HPETState *s = opaque;
@@ -455,7 +455,7 @@
return 0;
}
-static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
+static void hpet_ram_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int i;
diff --git a/hw/i82378.c b/hw/i82378.c
index 2123c14..99f35d4 100644
--- a/hw/i82378.c
+++ b/hw/i82378.c
@@ -59,7 +59,7 @@
},
};
-static void i82378_io_write(void *opaque, target_phys_addr_t addr,
+static void i82378_io_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
switch (size) {
@@ -83,7 +83,7 @@
}
}
-static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t i82378_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
@@ -105,7 +105,7 @@
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
+static void i82378_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
switch (size) {
@@ -129,7 +129,7 @@
}
}
-static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t i82378_mem_read(void *opaque, hwaddr addr,
unsigned int size)
{
DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
diff --git a/hw/i8259.c b/hw/i8259.c
index 53daf78..af0ba4d 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -235,7 +235,7 @@
pic_init_reset(s);
}
-static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
+static void pic_ioport_write(void *opaque, hwaddr addr64,
uint64_t val64, unsigned size)
{
PICCommonState *s = opaque;
@@ -329,7 +329,7 @@
}
}
-static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PICCommonState *s = opaque;
@@ -366,14 +366,14 @@
return (pic_get_irq(s) >= 0);
}
-static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
+static void elcr_ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PICCommonState *s = opaque;
s->elcr = val & s->elcr_mask;
}
-static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PICCommonState *s = opaque;
diff --git a/hw/ide.h b/hw/ide.h
index 2db4079..add742c 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -24,7 +24,7 @@
void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 68671bc..67562db 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -174,7 +174,7 @@
static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted)
{
- target_phys_addr_t len = wanted;
+ hwaddr len = wanted;
if (*ptr) {
cpu_physical_memory_unmap(*ptr, len, 1, len);
@@ -279,7 +279,7 @@
}
}
-static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
AHCIState *s = opaque;
@@ -317,7 +317,7 @@
-static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
+static void ahci_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;
@@ -373,7 +373,7 @@
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
unsigned size)
{
AHCIState *s = opaque;
@@ -389,7 +389,7 @@
}
}
-static void ahci_idp_write(void *opaque, target_phys_addr_t addr,
+static void ahci_idp_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index e0b9443..804db60 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -43,7 +43,7 @@
static void cmd646_update_irq(PCIIDEState *d);
-static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -54,7 +54,7 @@
return ide_status_read(cmd646bar->bus, addr + 2);
}
-static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
+static void cmd646_cmd_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -71,7 +71,7 @@
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -88,7 +88,7 @@
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
+static void cmd646_data_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -121,7 +121,7 @@
memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8);
}
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_read(void *opaque, hwaddr addr,
unsigned size)
{
BMDMAState *bm = opaque;
@@ -159,7 +159,7 @@
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index f228725..720af6e 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -198,7 +198,7 @@
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -216,7 +216,7 @@
}
}
-static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
@@ -238,7 +238,7 @@
}
static void pmac_ide_writew (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -249,7 +249,7 @@
}
}
-static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
@@ -265,7 +265,7 @@
}
static void pmac_ide_writel (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -276,7 +276,7 @@
}
}
-static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
{
uint32_t retval;
MACIOIDEState *d = opaque;
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
index fcfb09e..bcb26c8 100644
--- a/hw/ide/mmio.c
+++ b/hw/ide/mmio.c
@@ -47,7 +47,7 @@
ide_bus_reset(&s->bus);
}
-static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s = opaque;
@@ -58,7 +58,7 @@
return ide_data_readw(&s->bus, 0);
}
-static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
+static void mmio_ide_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
@@ -75,14 +75,14 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t mmio_ide_status_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s= opaque;
return ide_status_read(&s->bus, 0);
}
-static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
+static void mmio_ide_cmd_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
@@ -107,7 +107,7 @@
}
};
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+void mmio_ide_init (hwaddr membase, hwaddr membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 644533f..bcdd70e 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -327,7 +327,7 @@
bm->cmd = val & 0x09;
}
-static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
unsigned width)
{
BMDMAState *bm = opaque;
@@ -341,7 +341,7 @@
return data;
}
-static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_addr_write(void *opaque, hwaddr addr,
uint64_t data, unsigned width)
{
BMDMAState *bm = opaque;
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 4ded9ee..9431bad 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -33,7 +33,7 @@
#include <hw/ide/pci.h>
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
{
BMDMAState *bm = opaque;
uint32_t val;
@@ -59,7 +59,7 @@
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
diff --git a/hw/ide/via.c b/hw/ide/via.c
index b20e4f0..efda173 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -33,7 +33,7 @@
#include <hw/ide/pci.h>
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_read(void *opaque, hwaddr addr,
unsigned size)
{
BMDMAState *bm = opaque;
@@ -60,7 +60,7 @@
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
diff --git a/hw/imx.h b/hw/imx.h
index ccf586f..ea9e093 100644
--- a/hw/imx.h
+++ b/hw/imx.h
@@ -11,7 +11,7 @@
#ifndef IMX_H
#define IMX_H
-void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq);
+void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
typedef enum {
NOCLK,
@@ -23,10 +23,10 @@
uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
-void imx_timerp_create(const target_phys_addr_t addr,
+void imx_timerp_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);
-void imx_timerg_create(const target_phys_addr_t addr,
+void imx_timerg_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm);
diff --git a/hw/imx_avic.c b/hw/imx_avic.c
index b1a8fe6..8109793 100644
--- a/hw/imx_avic.c
+++ b/hw/imx_avic.c
@@ -152,7 +152,7 @@
static uint64_t imx_avic_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
IMXAVICState *s = (IMXAVICState *)opaque;
@@ -259,7 +259,7 @@
}
}
-static void imx_avic_write(void *opaque, target_phys_addr_t offset,
+static void imx_avic_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
IMXAVICState *s = (IMXAVICState *)opaque;
diff --git a/hw/imx_ccm.c b/hw/imx_ccm.c
index 10952c6..f2e623c 100644
--- a/hw/imx_ccm.c
+++ b/hw/imx_ccm.c
@@ -191,7 +191,7 @@
update_clocks(s);
}
-static uint64_t imx_ccm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXCCMState *s = (IMXCCMState *)opaque;
@@ -232,7 +232,7 @@
return 0;
}
-static void imx_ccm_write(void *opaque, target_phys_addr_t offset,
+static void imx_ccm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXCCMState *s = (IMXCCMState *)opaque;
diff --git a/hw/imx_serial.c b/hw/imx_serial.c
index d4eae43..dcd125f 100644
--- a/hw/imx_serial.c
+++ b/hw/imx_serial.c
@@ -183,7 +183,7 @@
}
-static uint64_t imx_serial_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_serial_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
@@ -244,7 +244,7 @@
}
}
-static void imx_serial_write(void *opaque, target_phys_addr_t offset,
+static void imx_serial_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
@@ -401,7 +401,7 @@
return 0;
}
-void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq)
+void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *bus;
@@ -427,7 +427,7 @@
qdev_prop_set_chr(dev, "chardev", chr);
bus = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(bus, 0, addr);
}
sysbus_connect_irq(bus, 0, irq);
diff --git a/hw/imx_timer.c b/hw/imx_timer.c
index c28c537..33f33fb 100644
--- a/hw/imx_timer.c
+++ b/hw/imx_timer.c
@@ -194,7 +194,7 @@
ptimer_set_count(s->timer, diff_cnt);
}
-static uint64_t imx_timerg_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXTimerGState *s = (IMXTimerGState *)opaque;
@@ -251,7 +251,7 @@
imx_timerg_set_freq(s);
}
-static void imx_timerg_write(void *opaque, target_phys_addr_t offset,
+static void imx_timerg_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXTimerGState *s = (IMXTimerGState *)opaque;
@@ -468,7 +468,7 @@
ptimer_set_count(s->timer, TIMER_MAX);
}
-static uint64_t imx_timerp_read(void *opaque, target_phys_addr_t offset,
+static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
@@ -517,7 +517,7 @@
}
}
-static void imx_timerp_write(void *opaque, target_phys_addr_t offset,
+static void imx_timerp_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
IMXTimerPState *s = (IMXTimerPState *)opaque;
@@ -580,7 +580,7 @@
imx_timerp_update(s);
}
-void imx_timerp_create(const target_phys_addr_t addr,
+void imx_timerp_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm)
{
@@ -634,7 +634,7 @@
}
-void imx_timerg_create(const target_phys_addr_t addr,
+void imx_timerg_create(const hwaddr addr,
qemu_irq irq,
DeviceState *ccm)
{
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index ac0ea83..77807c3 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -38,7 +38,7 @@
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
-static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t integratorcm_read(void *opaque, hwaddr offset,
unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
@@ -141,7 +141,7 @@
hw_error("Core module interrupt\n");
}
-static void integratorcm_write(void *opaque, target_phys_addr_t offset,
+static void integratorcm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
@@ -295,7 +295,7 @@
icp_pic_update(s);
}
-static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_pic_read(void *opaque, hwaddr offset,
unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@@ -324,7 +324,7 @@
}
}
-static void icp_pic_write(void *opaque, target_phys_addr_t offset,
+static void icp_pic_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@@ -381,7 +381,7 @@
/* CP control registers. */
-static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_control_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (offset >> 2) {
@@ -399,7 +399,7 @@
}
}
-static void icp_control_write(void *opaque, target_phys_addr_t offset,
+static void icp_control_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
switch (offset >> 2) {
@@ -419,7 +419,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void icp_control_init(target_phys_addr_t base)
+static void icp_control_init(hwaddr base)
{
MemoryRegion *io;
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index d8e1b23..a68c368 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -206,9 +206,9 @@
/* --------------------------------------------------------------------- */
-static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
+static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
{
- target_phys_addr_t addr;
+ hwaddr addr;
addr = ((uint64_t)ubase << 32) | lbase;
return addr;
@@ -295,7 +295,7 @@
static void intel_hda_corb_run(IntelHDAState *d)
{
- target_phys_addr_t addr;
+ hwaddr addr;
uint32_t rp, verb;
if (d->ics & ICH6_IRS_BUSY) {
@@ -332,7 +332,7 @@
{
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
- target_phys_addr_t addr;
+ hwaddr addr;
uint32_t wp, ex;
if (d->ics & ICH6_IRS_BUSY) {
@@ -381,7 +381,7 @@
{
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
- target_phys_addr_t addr;
+ hwaddr addr;
uint32_t s, copy, left;
IntelHDAStream *st;
bool irq = false;
@@ -453,7 +453,7 @@
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
{
- target_phys_addr_t addr;
+ hwaddr addr;
uint8_t buf[16];
uint32_t i;
@@ -890,7 +890,7 @@
};
-static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
+static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
{
const IntelHDAReg *reg;
@@ -1033,7 +1033,7 @@
/* --------------------------------------------------------------------- */
-static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1041,7 +1041,7 @@
intel_hda_reg_write(d, reg, val, 0xff);
}
-static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1049,7 +1049,7 @@
intel_hda_reg_write(d, reg, val, 0xffff);
}
-static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1057,7 +1057,7 @@
intel_hda_reg_write(d, reg, val, 0xffffffff);
}
-static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1065,7 +1065,7 @@
return intel_hda_reg_read(d, reg, 0xff);
}
-static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1073,7 +1073,7 @@
return intel_hda_reg_read(d, reg, 0xffff);
}
-static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
diff --git a/hw/ioapic.c b/hw/ioapic.c
index e2e4796..7273095 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -139,7 +139,7 @@
}
static uint64_t
-ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
{
IOAPICCommonState *s = opaque;
int index;
@@ -181,7 +181,7 @@
}
static void
-ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int size)
{
IOAPICCommonState *s = opaque;
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 214f194..685fdc0 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -24,7 +24,7 @@
#include "exec-memory.h"
static ISABus *isabus;
-target_phys_addr_t isa_mem_base = 0;
+hwaddr isa_mem_base = 0;
static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *isabus_get_fw_dev_path(DeviceState *dev);
diff --git a/hw/isa.h b/hw/isa.h
index 8fb498a..f9382e8 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -84,10 +84,10 @@
return DO_UPCAST(ISABus, qbus, d->qdev.parent_bus);
}
-extern target_phys_addr_t isa_mem_base;
+extern hwaddr isa_mem_base;
-void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size);
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
+void isa_mmio_setup(MemoryRegion *mr, hwaddr size);
+void isa_mmio_init(hwaddr base, hwaddr size);
/* dma.c */
int DMA_get_channel_mode (int nchan);
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index fd755ab..1405396 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -26,35 +26,35 @@
#include "isa.h"
#include "exec-memory.h"
-static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writeb (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writew(void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writel(void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
-static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readb (void *opaque, hwaddr addr)
{
return cpu_inb(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readw(void *opaque, hwaddr addr)
{
return cpu_inw(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readl(void *opaque, hwaddr addr)
{
return cpu_inl(addr & IOPORTS_MASK);
}
@@ -67,12 +67,12 @@
.endianness = DEVICE_LITTLE_ENDIAN,
};
-void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size)
+void isa_mmio_setup(MemoryRegion *mr, hwaddr size)
{
memory_region_init_io(mr, &isa_mmio_ops, NULL, "isa-mmio", size);
}
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
+void isa_mmio_init(hwaddr base, hwaddr size)
{
MemoryRegion *mr = g_malloc(sizeof(*mr));
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index 5c4ccb8..f6dbb21 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -163,7 +163,7 @@
return ret;
}
-static void ivshmem_io_write(void *opaque, target_phys_addr_t addr,
+static void ivshmem_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
IVShmemState *s = opaque;
@@ -202,7 +202,7 @@
}
}
-static uint64_t ivshmem_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
unsigned size)
{
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index 6486523..a6a90ab 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
@@ -39,7 +39,7 @@
screen_state_t state;
} LedState;
-static uint64_t jazz_led_read(void *opaque, target_phys_addr_t addr,
+static uint64_t jazz_led_read(void *opaque, hwaddr addr,
unsigned int size)
{
LedState *s = opaque;
@@ -51,7 +51,7 @@
return val;
}
-static void jazz_led_write(void *opaque, target_phys_addr_t addr,
+static void jazz_led_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
LedState *s = opaque;
diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c
index 80e3e48..dbac7ff 100644
--- a/hw/kvm/apic.c
+++ b/hw/kvm/apic.c
@@ -146,13 +146,13 @@
run_on_cpu(s->cpu_env, do_inject_external_nmi, s);
}
-static uint64_t kvm_apic_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return ~(uint64_t)0;
}
-static void kvm_apic_mem_write(void *opaque, target_phys_addr_t addr,
+static void kvm_apic_mem_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
MSIMessage msg = { .address = addr, .data = data };
diff --git a/hw/kvm/pci-assign.c b/hw/kvm/pci-assign.c
index 7a0998c..bfffbab 100644
--- a/hw/kvm/pci-assign.c
+++ b/hw/kvm/pci-assign.c
@@ -133,7 +133,7 @@
int msi_virq_nr;
int *msi_virq;
MSIXTableEntry *msix_table;
- target_phys_addr_t msix_table_addr;
+ hwaddr msix_table_addr;
uint16_t msix_max;
MemoryRegion mmio;
char *configfd_name;
@@ -147,7 +147,7 @@
static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev);
static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
- target_phys_addr_t addr, int size,
+ hwaddr addr, int size,
uint64_t *data)
{
uint64_t val = 0;
@@ -206,19 +206,19 @@
return val;
}
-static void assigned_dev_ioport_write(void *opaque, target_phys_addr_t addr,
+static void assigned_dev_ioport_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
assigned_dev_ioport_rw(opaque, addr, size, &data);
}
static uint64_t assigned_dev_ioport_read(void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
return assigned_dev_ioport_rw(opaque, addr, size, NULL);
}
-static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readb(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint8_t *in = d->u.r_virtbase + addr;
@@ -230,7 +230,7 @@
return r;
}
-static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readw(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint16_t *in = (uint16_t *)(d->u.r_virtbase + addr);
@@ -242,7 +242,7 @@
return r;
}
-static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readl(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint32_t *in = (uint32_t *)(d->u.r_virtbase + addr);
@@ -254,7 +254,7 @@
return r;
}
-static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writeb(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint8_t *out = d->u.r_virtbase + addr;
@@ -263,7 +263,7 @@
*out = val;
}
-static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writew(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint16_t *out = (uint16_t *)(d->u.r_virtbase + addr);
@@ -272,7 +272,7 @@
*out = val;
}
-static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writel(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint32_t *out = (uint32_t *)(d->u.r_virtbase + addr);
@@ -1499,7 +1499,7 @@
}
static uint64_t
-assigned_dev_msix_mmio_read(void *opaque, target_phys_addr_t addr,
+assigned_dev_msix_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
AssignedDevice *adev = opaque;
@@ -1510,7 +1510,7 @@
return val;
}
-static void assigned_dev_msix_mmio_write(void *opaque, target_phys_addr_t addr,
+static void assigned_dev_msix_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AssignedDevice *adev = opaque;
diff --git a/hw/kvmvapic.c b/hw/kvmvapic.c
index 5d83625..5e0a7c9 100644
--- a/hw/kvmvapic.c
+++ b/hw/kvmvapic.c
@@ -144,7 +144,7 @@
static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
target_ulong addr;
if (s->state == VAPIC_ACTIVE) {
@@ -269,7 +269,7 @@
static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
uint32_t rom_state_vaddr;
uint32_t pos, patch, offset;
@@ -350,14 +350,14 @@
static int vapic_enable(VAPICROMState *s, CPUX86State *env)
{
int cpu_number = get_kpcr_number(env);
- target_phys_addr_t vapic_paddr;
+ hwaddr vapic_paddr;
static const uint8_t enabled = 1;
if (cpu_number < 0) {
return -1;
}
vapic_paddr = s->vapic_paddr +
- (((target_phys_addr_t)cpu_number) << VAPIC_CPU_SHIFT);
+ (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
(void *)&enabled, sizeof(enabled), 1);
apic_enable_vapic(env->apic_state, vapic_paddr);
@@ -384,7 +384,7 @@
static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
- target_phys_addr_t paddr;
+ hwaddr paddr;
VAPICHandlers *handlers;
uint8_t opcode[2];
uint32_t imm32;
@@ -500,7 +500,7 @@
*/
static int patch_hypercalls(VAPICROMState *s)
{
- target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
+ hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
static const uint8_t vmcall_pattern[] = { /* vmcall */
0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
};
@@ -557,7 +557,7 @@
*/
static void vapic_map_rom_writable(VAPICROMState *s)
{
- target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
+ hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
MemoryRegionSection section;
MemoryRegion *as;
size_t rom_size;
@@ -603,11 +603,11 @@
return 0;
}
-static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data,
+static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
unsigned int size)
{
CPUX86State *env = cpu_single_env;
- target_phys_addr_t rom_paddr;
+ hwaddr rom_paddr;
VAPICROMState *s = opaque;
cpu_synchronize_state(env);
diff --git a/hw/lan9118.c b/hw/lan9118.c
index ceaf96f..f724e1c 100644
--- a/hw/lan9118.c
+++ b/hw/lan9118.c
@@ -1000,7 +1000,7 @@
lan9118_update(s);
}
-static void lan9118_writel(void *opaque, target_phys_addr_t offset,
+static void lan9118_writel(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
lan9118_state *s = (lan9118_state *)opaque;
@@ -1134,7 +1134,7 @@
lan9118_update(s);
}
-static void lan9118_writew(void *opaque, target_phys_addr_t offset,
+static void lan9118_writew(void *opaque, hwaddr offset,
uint32_t val)
{
lan9118_state *s = (lan9118_state *)opaque;
@@ -1161,7 +1161,7 @@
}
}
-static void lan9118_16bit_mode_write(void *opaque, target_phys_addr_t offset,
+static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
switch (size) {
@@ -1176,7 +1176,7 @@
hw_error("lan9118_write: Bad size 0x%x\n", size);
}
-static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
+static uint64_t lan9118_readl(void *opaque, hwaddr offset,
unsigned size)
{
lan9118_state *s = (lan9118_state *)opaque;
@@ -1250,7 +1250,7 @@
return 0;
}
-static uint32_t lan9118_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t lan9118_readw(void *opaque, hwaddr offset)
{
lan9118_state *s = (lan9118_state *)opaque;
uint32_t val;
@@ -1278,7 +1278,7 @@
return val;
}
-static uint64_t lan9118_16bit_mode_read(void *opaque, target_phys_addr_t offset,
+static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (size) {
diff --git a/hw/lance.c b/hw/lance.c
index 9b98bb8..a3e6dd9 100644
--- a/hw/lance.c
+++ b/hw/lance.c
@@ -55,7 +55,7 @@
pcnet_h_reset(&d->state);
}
-static void lance_mem_write(void *opaque, target_phys_addr_t addr,
+static void lance_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SysBusPCNetState *d = opaque;
@@ -64,7 +64,7 @@
pcnet_ioport_writew(&d->state, addr, val & 0xffff);
}
-static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lance_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SysBusPCNetState *d = opaque;
diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
index c5a62c8..772cb8b 100644
--- a/hw/lm32_boards.c
+++ b/hw/lm32_boards.c
@@ -32,12 +32,12 @@
typedef struct {
LM32CPU *cpu;
- target_phys_addr_t bootstrap_pc;
- target_phys_addr_t flash_base;
- target_phys_addr_t hwsetup_base;
- target_phys_addr_t initrd_base;
+ hwaddr bootstrap_pc;
+ hwaddr flash_base;
+ hwaddr hwsetup_base;
+ hwaddr initrd_base;
size_t initrd_size;
- target_phys_addr_t cmdline_base;
+ hwaddr cmdline_base;
} ResetInfo;
static void cpu_irq_handler(void *opaque, int irq, int level)
@@ -83,14 +83,14 @@
int i;
/* memory map */
- target_phys_addr_t flash_base = 0x04000000;
+ hwaddr flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t ram_base = 0x08000000;
+ hwaddr ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024;
- target_phys_addr_t timer0_base = 0x80002000;
- target_phys_addr_t uart0_base = 0x80006000;
- target_phys_addr_t timer1_base = 0x8000a000;
+ hwaddr timer0_base = 0x80002000;
+ hwaddr uart0_base = 0x80006000;
+ hwaddr timer1_base = 0x8000a000;
int uart0_irq = 0;
int timer0_irq = 1;
int timer1_irq = 3;
@@ -174,22 +174,22 @@
int i;
/* memory map */
- target_phys_addr_t flash_base = 0x04000000;
+ hwaddr flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t ram_base = 0x08000000;
+ hwaddr ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024;
- target_phys_addr_t uart0_base = 0x80000000;
- target_phys_addr_t timer0_base = 0x80002000;
- target_phys_addr_t timer1_base = 0x80010000;
- target_phys_addr_t timer2_base = 0x80012000;
+ hwaddr uart0_base = 0x80000000;
+ hwaddr timer0_base = 0x80002000;
+ hwaddr timer1_base = 0x80010000;
+ hwaddr timer2_base = 0x80012000;
int uart0_irq = 0;
int timer0_irq = 1;
int timer1_irq = 20;
int timer2_irq = 21;
- target_phys_addr_t hwsetup_base = 0x0bffe000;
- target_phys_addr_t cmdline_base = 0x0bfff000;
- target_phys_addr_t initrd_base = 0x08400000;
+ hwaddr hwsetup_base = 0x0bffe000;
+ hwaddr cmdline_base = 0x0bfff000;
+ hwaddr initrd_base = 0x08400000;
size_t initrd_max = 0x01000000;
reset_info = g_malloc0(sizeof(ResetInfo));
diff --git a/hw/lm32_hwsetup.h b/hw/lm32_hwsetup.h
index 70dc61f..853e9ab 100644
--- a/hw/lm32_hwsetup.h
+++ b/hw/lm32_hwsetup.h
@@ -71,7 +71,7 @@
}
static inline void hwsetup_create_rom(HWSetup *hw,
- target_phys_addr_t base)
+ hwaddr base)
{
rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
}
diff --git a/hw/lm32_sys.c b/hw/lm32_sys.c
index bbe03c4..a7887d1 100644
--- a/hw/lm32_sys.c
+++ b/hw/lm32_sys.c
@@ -61,7 +61,7 @@
s->testname[MAX_TESTNAME_LEN - 1] = '\0';
}
-static void sys_write(void *opaque, target_phys_addr_t addr,
+static void sys_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32SysState *s = opaque;
@@ -91,7 +91,7 @@
}
}
-static bool sys_ops_accepts(void *opaque, target_phys_addr_t addr,
+static bool sys_ops_accepts(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write && size == 4;
diff --git a/hw/lm32_timer.c b/hw/lm32_timer.c
index e9450a0..a8be9cc 100644
--- a/hw/lm32_timer.c
+++ b/hw/lm32_timer.c
@@ -72,7 +72,7 @@
qemu_set_irq(s->irq, state);
}
-static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
{
LM32TimerState *s = opaque;
uint32_t r = 0;
@@ -97,7 +97,7 @@
return r;
}
-static void timer_write(void *opaque, target_phys_addr_t addr,
+static void timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32TimerState *s = opaque;
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
index 57066e2..adb9287 100644
--- a/hw/lm32_uart.c
+++ b/hw/lm32_uart.c
@@ -125,7 +125,7 @@
qemu_set_irq(s->irq, irq);
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned size)
{
LM32UartState *s = opaque;
@@ -160,7 +160,7 @@
return r;
}
-static void uart_write(void *opaque, target_phys_addr_t addr,
+static void uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32UartState *s = opaque;
diff --git a/hw/lm4549.c b/hw/lm4549.c
index e0137d5..b3c2d5f 100644
--- a/hw/lm4549.c
+++ b/hw/lm4549.c
@@ -150,7 +150,7 @@
}
}
-uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset)
+uint32_t lm4549_read(lm4549_state *s, hwaddr offset)
{
uint16_t *regfile = s->regfile;
uint32_t value = 0;
@@ -165,7 +165,7 @@
}
void lm4549_write(lm4549_state *s,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
uint16_t *regfile = s->regfile;
diff --git a/hw/lm4549.h b/hw/lm4549.h
index 5948780..812a7a4 100644
--- a/hw/lm4549.h
+++ b/hw/lm4549.h
@@ -36,8 +36,8 @@
void lm4549_init(lm4549_state *s, lm4549_callback data_req, void *opaque);
-uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset);
-void lm4549_write(lm4549_state *s, target_phys_addr_t offset, uint32_t value);
+uint32_t lm4549_read(lm4549_state *s, hwaddr offset);
+void lm4549_write(lm4549_state *s, hwaddr offset, uint32_t value);
uint32_t lm4549_write_samples(lm4549_state *s, uint32_t left, uint32_t right);
#endif /* #ifndef HW_LM4549_H */
diff --git a/hw/loader.c b/hw/loader.c
index 33acc2f..ba01ca6 100644
--- a/hw/loader.c
+++ b/hw/loader.c
@@ -88,7 +88,7 @@
/* read()-like version */
ssize_t read_targphys(const char *name,
- int fd, target_phys_addr_t dst_addr, size_t nbytes)
+ int fd, hwaddr dst_addr, size_t nbytes)
{
uint8_t *buf;
ssize_t did;
@@ -103,7 +103,7 @@
/* return the size or -1 if error */
int load_image_targphys(const char *filename,
- target_phys_addr_t addr, uint64_t max_sz)
+ hwaddr addr, uint64_t max_sz)
{
int size;
@@ -117,7 +117,7 @@
return size;
}
-void pstrcpy_targphys(const char *name, target_phys_addr_t dest, int buf_size,
+void pstrcpy_targphys(const char *name, hwaddr dest, int buf_size,
const char *source)
{
const char *nulp;
@@ -179,8 +179,8 @@
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
- int bswap_needed, target_phys_addr_t target_page_size)
+int load_aout(const char *filename, hwaddr addr, int max_sz,
+ int bswap_needed, hwaddr target_page_size)
{
int fd;
ssize_t size, ret;
@@ -434,8 +434,8 @@
}
/* Load a U-Boot image. */
-int load_uimage(const char *filename, target_phys_addr_t *ep,
- target_phys_addr_t *loadaddr, int *is_linux)
+int load_uimage(const char *filename, hwaddr *ep,
+ hwaddr *loadaddr, int *is_linux)
{
int fd;
int size;
@@ -539,7 +539,7 @@
char *fw_dir;
char *fw_file;
- target_phys_addr_t addr;
+ hwaddr addr;
QTAILQ_ENTRY(Rom) next;
};
@@ -565,7 +565,7 @@
}
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr, int32_t bootindex)
+ hwaddr addr, int32_t bootindex)
{
Rom *rom;
int rc, fd = -1;
@@ -633,7 +633,7 @@
}
int rom_add_blob(const char *name, const void *blob, size_t len,
- target_phys_addr_t addr)
+ hwaddr addr)
{
Rom *rom;
@@ -679,7 +679,7 @@
int rom_load_all(void)
{
- target_phys_addr_t addr = 0;
+ hwaddr addr = 0;
MemoryRegionSection section;
Rom *rom;
@@ -709,7 +709,7 @@
fw_cfg = f;
}
-static Rom *find_rom(target_phys_addr_t addr)
+static Rom *find_rom(hwaddr addr)
{
Rom *rom;
@@ -733,9 +733,9 @@
* a ROM between addr and addr + size is copied. Note that this can involve
* multiple ROMs, which need not start at addr and need not end at addr + size.
*/
-int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size)
+int rom_copy(uint8_t *dest, hwaddr addr, size_t size)
{
- target_phys_addr_t end = addr + size;
+ hwaddr end = addr + size;
uint8_t *s, *d = dest;
size_t l = 0;
Rom *rom;
@@ -768,7 +768,7 @@
return (d + l) - dest;
}
-void *rom_ptr(target_phys_addr_t addr)
+void *rom_ptr(hwaddr addr)
{
Rom *rom;
diff --git a/hw/loader.h b/hw/loader.h
index 6da291e..26480ad 100644
--- a/hw/loader.h
+++ b/hw/loader.h
@@ -4,32 +4,32 @@
/* loader.c */
int get_image_size(const char *filename);
int load_image(const char *filename, uint8_t *addr); /* deprecated */
-int load_image_targphys(const char *filename, target_phys_addr_t,
+int load_image_targphys(const char *filename, hwaddr,
uint64_t max_sz);
int load_elf(const char *filename, uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque, uint64_t *pentry, uint64_t *lowaddr,
uint64_t *highaddr, int big_endian, int elf_machine,
int clear_lsb);
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
- int bswap_needed, target_phys_addr_t target_page_size);
-int load_uimage(const char *filename, target_phys_addr_t *ep,
- target_phys_addr_t *loadaddr, int *is_linux);
+int load_aout(const char *filename, hwaddr addr, int max_sz,
+ int bswap_needed, hwaddr target_page_size);
+int load_uimage(const char *filename, hwaddr *ep,
+ hwaddr *loadaddr, int *is_linux);
ssize_t read_targphys(const char *name,
- int fd, target_phys_addr_t dst_addr, size_t nbytes);
+ int fd, hwaddr dst_addr, size_t nbytes);
void pstrcpy_targphys(const char *name,
- target_phys_addr_t dest, int buf_size,
+ hwaddr dest, int buf_size,
const char *source);
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr, int32_t bootindex);
+ hwaddr addr, int32_t bootindex);
int rom_add_blob(const char *name, const void *blob, size_t len,
- target_phys_addr_t addr);
+ hwaddr addr);
int rom_load_all(void);
void rom_set_fw(void *f);
-int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size);
-void *rom_ptr(target_phys_addr_t addr);
+int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
+void *rom_ptr(hwaddr addr);
void do_info_roms(Monitor *mon);
#define rom_add_file_fixed(_f, _a, _i) \
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index 34afe96..04f2fae 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -1878,7 +1878,7 @@
#undef CASE_SET_REG32
}
-static void lsi_mmio_write(void *opaque, target_phys_addr_t addr,
+static void lsi_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
@@ -1886,7 +1886,7 @@
lsi_reg_writeb(s, addr & 0xff, val);
}
-static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
LSIState *s = opaque;
@@ -1904,7 +1904,7 @@
},
};
-static void lsi_ram_write(void *opaque, target_phys_addr_t addr,
+static void lsi_ram_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
@@ -1920,7 +1920,7 @@
s->script_ram[addr >> 2] = newval;
}
-static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_ram_read(void *opaque, hwaddr addr,
unsigned size)
{
LSIState *s = opaque;
@@ -1939,14 +1939,14 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t lsi_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_io_read(void *opaque, hwaddr addr,
unsigned size)
{
LSIState *s = opaque;
return lsi_reg_readb(s, addr & 0xff);
}
-static void lsi_io_write(void *opaque, target_phys_addr_t addr,
+static void lsi_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
diff --git a/hw/m48t59.c b/hw/m48t59.c
index dd6cb37..9eb1a09 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -522,14 +522,14 @@
return retval;
}
-static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
-static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
@@ -537,7 +537,7 @@
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
-static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
@@ -547,7 +547,7 @@
m48t59_write(NVRAM, addr + 3, value & 0xff);
}
-static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readb (void *opaque, hwaddr addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
@@ -556,7 +556,7 @@
return retval;
}
-static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readw (void *opaque, hwaddr addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
@@ -566,7 +566,7 @@
return retval;
}
-static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readl (void *opaque, hwaddr addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
@@ -636,7 +636,7 @@
};
/* Initialisation routine */
-M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int model)
{
DeviceState *dev;
diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
index 1791ec1..e551156 100644
--- a/hw/mac_dbdma.c
+++ b/hw/mac_dbdma.c
@@ -699,7 +699,7 @@
ch->flush(&ch->io);
}
-static void dbdma_write(void *opaque, target_phys_addr_t addr,
+static void dbdma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int channel = addr >> DBDMA_CHANNEL_SHIFT;
@@ -749,7 +749,7 @@
}
}
-static uint64_t dbdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dbdma_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t value;
diff --git a/hw/mac_dbdma.h b/hw/mac_dbdma.h
index 6d1abe6..bfdb0dd 100644
--- a/hw/mac_dbdma.h
+++ b/hw/mac_dbdma.h
@@ -30,7 +30,7 @@
struct DBDMA_io {
void *opaque;
void *channel;
- target_phys_addr_t addr;
+ hwaddr addr;
int len;
int is_last;
int is_dma_out;
diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
index ed0a2b7..a0d14dd 100644
--- a/hw/mac_nvram.c
+++ b/hw/mac_nvram.c
@@ -71,7 +71,7 @@
}
/* macio style NVRAM device */
-static void macio_nvram_writeb(void *opaque, target_phys_addr_t addr,
+static void macio_nvram_writeb(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
MacIONVRAMState *s = opaque;
@@ -81,7 +81,7 @@
NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
}
-static uint64_t macio_nvram_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
unsigned size)
{
MacIONVRAMState *s = opaque;
@@ -116,7 +116,7 @@
{
}
-MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
+MacIONVRAMState *macio_nvram_init (hwaddr size,
unsigned int it_shift)
{
MacIONVRAMState *s;
@@ -135,7 +135,7 @@
}
void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
- target_phys_addr_t mem_base)
+ hwaddr mem_base)
{
memory_region_add_subregion(bar, mem_base, &s->mem);
}
diff --git a/hw/mainstone.c b/hw/mainstone.c
index c0d6034..3266946 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -101,7 +101,7 @@
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
uint32_t sector_len = 256 * 1024;
- target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
+ hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *mpu;
DeviceState *mst_irq;
DriveInfo *dinfo;
diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c
index f6f1937..de16cfa 100644
--- a/hw/marvell_88w8618_audio.c
+++ b/hw/marvell_88w8618_audio.c
@@ -138,7 +138,7 @@
wm8750_set_bclk_in(s->wm, rate);
}
-static uint64_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_audio_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_audio_state *s = opaque;
@@ -164,7 +164,7 @@
}
}
-static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_audio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_audio_state *s = opaque;
diff --git a/hw/mcf.h b/hw/mcf.h
index 19a8b54..f929910 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -5,23 +5,23 @@
struct MemoryRegion;
/* mcf_uart.c */
-uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+uint64_t mcf_uart_read(void *opaque, hwaddr addr,
unsigned size);
-void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+void mcf_uart_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(struct MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
CPUM68KState *env);
/* mcf_fec.c */
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
- target_phys_addr_t base, qemu_irq *irq);
+ hwaddr base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index 27753e2..510d770 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -371,10 +371,10 @@
/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
-static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
-static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
+static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset);
+static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset);
-static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readb(void *opaque, hwaddr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
@@ -392,7 +392,7 @@
return m5206_mbar_read(s, offset, 1);
}
-static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@@ -416,7 +416,7 @@
return m5206_mbar_read(s, offset, 2);
}
-static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@@ -434,12 +434,12 @@
return m5206_mbar_read(s, offset, 4);
}
-static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writew(void *opaque, hwaddr offset,
uint32_t value);
-static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writel(void *opaque, hwaddr offset,
uint32_t value);
-static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@@ -463,7 +463,7 @@
m5206_mbar_write(s, offset, value, 1);
}
-static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writew(void *opaque, hwaddr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@@ -491,7 +491,7 @@
m5206_mbar_write(s, offset, value, 2);
}
-static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writel(void *opaque, hwaddr offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 688bc3c..b1db549 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -45,7 +45,7 @@
qemu_irq_lower(s->irq);
}
-static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
+static void m5208_timer_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
@@ -107,7 +107,7 @@
m5208_timer_update(s);
}
-static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
@@ -130,7 +130,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
+static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
unsigned size)
{
switch (addr) {
@@ -152,7 +152,7 @@
}
}
-static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
+static void m5208_sys_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
@@ -195,7 +195,7 @@
CPUM68KState *env;
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
qemu_irq *pic;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
index 2fec5bc..1ed193c 100644
--- a/hw/mcf_fec.c
+++ b/hw/mcf_fec.c
@@ -216,7 +216,7 @@
s->rfsr = 0x500;
}
-static uint64_t mcf_fec_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
@@ -254,7 +254,7 @@
}
}
-static void mcf_fec_write(void *opaque, target_phys_addr_t addr,
+static void mcf_fec_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
@@ -458,7 +458,7 @@
};
void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd,
- target_phys_addr_t base, qemu_irq *irq)
+ hwaddr base, qemu_irq *irq)
{
mcf_fec_state *s;
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index cc1a5f3..6ef6dac 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -43,7 +43,7 @@
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
-static uint64_t mcf_intc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
unsigned size)
{
int offset;
@@ -76,7 +76,7 @@
}
}
-static void mcf_intc_write(void *opaque, target_phys_addr_t addr,
+static void mcf_intc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
int offset;
@@ -138,7 +138,7 @@
};
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
CPUM68KState *env)
{
mcf_intc_state *s;
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index ec6a87f..d1655f8 100644
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -66,7 +66,7 @@
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
-uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+uint64_t mcf_uart_read(void *opaque, hwaddr addr,
unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
@@ -185,7 +185,7 @@
}
}
-void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+void mcf_uart_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
@@ -294,7 +294,7 @@
};
void mcf_uart_mm_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq,
CharDriverState *chr)
{
diff --git a/hw/megasas.c b/hw/megasas.c
index 0e57740..7a2036e 100644
--- a/hw/megasas.c
+++ b/hw/megasas.c
@@ -59,8 +59,8 @@
uint16_t count;
uint64_t context;
- target_phys_addr_t pa;
- target_phys_addr_t pa_size;
+ hwaddr pa;
+ hwaddr pa_size;
union mfi_frame *frame;
SCSIRequest *req;
QEMUSGList qsg;
@@ -277,7 +277,7 @@
uint8_t sense_len)
{
uint32_t pa_hi = 0, pa_lo;
- target_phys_addr_t pa;
+ hwaddr pa;
if (sense_len > cmd->frame->header.sense_len) {
sense_len = cmd->frame->header.sense_len;
@@ -404,7 +404,7 @@
}
static MegasasCmd *megasas_lookup_frame(MegasasState *s,
- target_phys_addr_t frame)
+ hwaddr frame)
{
MegasasCmd *cmd = NULL;
int num = 0, index;
@@ -424,7 +424,7 @@
}
static MegasasCmd *megasas_next_frame(MegasasState *s,
- target_phys_addr_t frame)
+ hwaddr frame)
{
MegasasCmd *cmd = NULL;
int num = 0, index;
@@ -452,11 +452,11 @@
}
static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
- target_phys_addr_t frame, uint64_t context, int count)
+ hwaddr frame, uint64_t context, int count)
{
MegasasCmd *cmd = NULL;
int frame_size = MFI_FRAME_SIZE * 16;
- target_phys_addr_t frame_size_p = frame_size;
+ hwaddr frame_size_p = frame_size;
cmd = megasas_next_frame(s, frame);
/* All frames busy */
@@ -561,7 +561,7 @@
static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
{
uint32_t pa_hi, pa_lo;
- target_phys_addr_t iq_pa, initq_size;
+ hwaddr iq_pa, initq_size;
struct mfi_init_qinfo *initq;
uint32_t flags;
int ret = MFI_STAT_OK;
@@ -1771,7 +1771,7 @@
static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
{
uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
- target_phys_addr_t abort_addr, addr_hi, addr_lo;
+ hwaddr abort_addr, addr_hi, addr_lo;
MegasasCmd *abort_cmd;
addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
@@ -1861,7 +1861,7 @@
}
}
-static uint64_t megasas_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
MegasasState *s = opaque;
@@ -1897,7 +1897,7 @@
return retval;
}
-static void megasas_mmio_write(void *opaque, target_phys_addr_t addr,
+static void megasas_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MegasasState *s = opaque;
@@ -1977,13 +1977,13 @@
}
};
-static uint64_t megasas_port_read(void *opaque, target_phys_addr_t addr,
+static uint64_t megasas_port_read(void *opaque, hwaddr addr,
unsigned size)
{
return megasas_mmio_read(opaque, addr & 0xff, size);
}
-static void megasas_port_write(void *opaque, target_phys_addr_t addr,
+static void megasas_port_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
megasas_mmio_write(opaque, addr & 0xff, val, size);
@@ -1999,7 +1999,7 @@
}
};
-static uint64_t megasas_queue_read(void *opaque, target_phys_addr_t addr,
+static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
unsigned size)
{
return 0;
diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c
index 1030e9c..02c349c 100644
--- a/hw/microblaze_boot.c
+++ b/hw/microblaze_boot.c
@@ -55,7 +55,7 @@
}
}
-static int microblaze_load_dtb(target_phys_addr_t addr,
+static int microblaze_load_dtb(hwaddr addr,
uint32_t ramsize,
const char *kernel_cmdline,
const char *dtb_filename)
@@ -100,7 +100,7 @@
return addr - 0x30000000LL;
}
-void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
+void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(MicroBlazeCPU *))
{
@@ -149,7 +149,7 @@
/* If it wasn't an ELF image, try an u-boot image. */
if (kernel_size < 0) {
- target_phys_addr_t uentry, loadaddr;
+ hwaddr uentry, loadaddr;
kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0);
boot_info.bootstrap_pc = uentry;
diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h
index c9a3064..c1cf836 100644
--- a/hw/microblaze_boot.h
+++ b/hw/microblaze_boot.h
@@ -3,7 +3,7 @@
#include "hw.h"
-void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
+void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(MicroBlazeCPU *));
diff --git a/hw/milkymist-ac97.c b/hw/milkymist-ac97.c
index 4414f39..d87656c 100644
--- a/hw/milkymist-ac97.c
+++ b/hw/milkymist-ac97.c
@@ -83,7 +83,7 @@
}
}
-static uint64_t ac97_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ac97_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistAC97State *s = opaque;
@@ -115,7 +115,7 @@
return r;
}
-static void ac97_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void ac97_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistAC97State *s = opaque;
diff --git a/hw/milkymist-hpdmc.c b/hw/milkymist-hpdmc.c
index 2da0293..5d120a4 100644
--- a/hw/milkymist-hpdmc.c
+++ b/hw/milkymist-hpdmc.c
@@ -48,7 +48,7 @@
};
typedef struct MilkymistHpdmcState MilkymistHpdmcState;
-static uint64_t hpdmc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t hpdmc_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistHpdmcState *s = opaque;
@@ -74,7 +74,7 @@
return r;
}
-static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void hpdmc_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistHpdmcState *s = opaque;
diff --git a/hw/milkymist-hw.h b/hw/milkymist-hw.h
index 9f358a7..96b2a7f 100644
--- a/hw/milkymist-hw.h
+++ b/hw/milkymist-hw.h
@@ -4,7 +4,7 @@
#include "qdev.h"
#include "qdev-addr.h"
-static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_uart_create(hwaddr base,
qemu_irq irq)
{
DeviceState *dev;
@@ -17,7 +17,7 @@
return dev;
}
-static inline DeviceState *milkymist_hpdmc_create(target_phys_addr_t base)
+static inline DeviceState *milkymist_hpdmc_create(hwaddr base)
{
DeviceState *dev;
@@ -28,7 +28,7 @@
return dev;
}
-static inline DeviceState *milkymist_memcard_create(target_phys_addr_t base)
+static inline DeviceState *milkymist_memcard_create(hwaddr base)
{
DeviceState *dev;
@@ -39,7 +39,7 @@
return dev;
}
-static inline DeviceState *milkymist_vgafb_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_vgafb_create(hwaddr base,
uint32_t fb_offset, uint32_t fb_mask)
{
DeviceState *dev;
@@ -53,7 +53,7 @@
return dev;
}
-static inline DeviceState *milkymist_sysctl_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_sysctl_create(hwaddr base,
qemu_irq gpio_irq, qemu_irq timer0_irq, qemu_irq timer1_irq,
uint32_t freq_hz, uint32_t system_id, uint32_t capabilities,
uint32_t gpio_strappings)
@@ -74,7 +74,7 @@
return dev;
}
-static inline DeviceState *milkymist_pfpu_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_pfpu_create(hwaddr base,
qemu_irq irq)
{
DeviceState *dev;
@@ -97,7 +97,7 @@
};
#endif
-static inline DeviceState *milkymist_tmu2_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_tmu2_create(hwaddr base,
qemu_irq irq)
{
#ifdef CONFIG_OPENGL
@@ -152,7 +152,7 @@
#endif
}
-static inline DeviceState *milkymist_ac97_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_ac97_create(hwaddr base,
qemu_irq crrequest_irq, qemu_irq crreply_irq, qemu_irq dmar_irq,
qemu_irq dmaw_irq)
{
@@ -169,7 +169,7 @@
return dev;
}
-static inline DeviceState *milkymist_minimac_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_minimac_create(hwaddr base,
qemu_irq rx_irq, qemu_irq tx_irq)
{
DeviceState *dev;
@@ -185,8 +185,8 @@
return dev;
}
-static inline DeviceState *milkymist_minimac2_create(target_phys_addr_t base,
- target_phys_addr_t buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
+static inline DeviceState *milkymist_minimac2_create(hwaddr base,
+ hwaddr buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
{
DeviceState *dev;
@@ -202,7 +202,7 @@
return dev;
}
-static inline DeviceState *milkymist_softusb_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_softusb_create(hwaddr base,
qemu_irq irq, uint32_t pmem_base, uint32_t pmem_size,
uint32_t dmem_base, uint32_t dmem_size)
{
diff --git a/hw/milkymist-memcard.c b/hw/milkymist-memcard.c
index 3515c3c..ca5df56 100644
--- a/hw/milkymist-memcard.c
+++ b/hw/milkymist-memcard.c
@@ -117,7 +117,7 @@
}
}
-static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
+static uint64_t memcard_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistMemcardState *s = opaque;
@@ -166,7 +166,7 @@
return r;
}
-static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistMemcardState *s = opaque;
diff --git a/hw/milkymist-minimac2.c b/hw/milkymist-minimac2.c
index b483a02..b204e5f 100644
--- a/hw/milkymist-minimac2.c
+++ b/hw/milkymist-minimac2.c
@@ -96,7 +96,7 @@
NICState *nic;
NICConf conf;
char *phy_model;
- target_phys_addr_t buffers_base;
+ hwaddr buffers_base;
MemoryRegion buffers;
MemoryRegion regs_region;
@@ -323,7 +323,7 @@
}
static uint64_t
-minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
+minimac2_read(void *opaque, hwaddr addr, unsigned size)
{
MilkymistMinimac2State *s = opaque;
uint32_t r = 0;
@@ -352,7 +352,7 @@
}
static void
-minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+minimac2_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistMinimac2State *s = opaque;
diff --git a/hw/milkymist-pfpu.c b/hw/milkymist-pfpu.c
index 0f9ff4a..450bab9 100644
--- a/hw/milkymist-pfpu.c
+++ b/hw/milkymist-pfpu.c
@@ -131,7 +131,7 @@
};
typedef struct MilkymistPFPUState MilkymistPFPUState;
-static inline target_phys_addr_t
+static inline hwaddr
get_dma_address(uint32_t base, uint32_t x, uint32_t y)
{
return base + 8 * (128 * y + x);
@@ -225,7 +225,7 @@
{
uint32_t a = cpu_to_be32(s->gp_regs[reg_a]);
uint32_t b = cpu_to_be32(s->gp_regs[reg_b]);
- target_phys_addr_t dma_ptr =
+ hwaddr dma_ptr =
get_dma_address(s->regs[R_MESHBASE],
s->gp_regs[GPR_X], s->gp_regs[GPR_Y]);
cpu_physical_memory_write(dma_ptr, (uint8_t *)&a, 4);
@@ -380,7 +380,7 @@
return (512 * s->regs[R_CODEPAGE]) + addr - MICROCODE_BEGIN;
}
-static uint64_t pfpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pfpu_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistPFPUState *s = opaque;
@@ -420,7 +420,7 @@
return r;
}
-static void pfpu_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void pfpu_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistPFPUState *s = opaque;
diff --git a/hw/milkymist-softusb.c b/hw/milkymist-softusb.c
index ecc2be9..b162b88 100644
--- a/hw/milkymist-softusb.c
+++ b/hw/milkymist-softusb.c
@@ -71,7 +71,7 @@
};
typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
-static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t softusb_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
@@ -95,7 +95,7 @@
}
static void
-softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+softusb_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
diff --git a/hw/milkymist-sysctl.c b/hw/milkymist-sysctl.c
index 8878d2b..f951ef9 100644
--- a/hw/milkymist-sysctl.c
+++ b/hw/milkymist-sysctl.c
@@ -89,7 +89,7 @@
}
}
-static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sysctl_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistSysctlState *s = opaque;
@@ -134,7 +134,7 @@
return r;
}
-static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistSysctlState *s = opaque;
diff --git a/hw/milkymist-tmu2.c b/hw/milkymist-tmu2.c
index 210ceed..3f9a684 100644
--- a/hw/milkymist-tmu2.c
+++ b/hw/milkymist-tmu2.c
@@ -182,9 +182,9 @@
GLXPbuffer pbuffer;
GLuint texture;
void *fb;
- target_phys_addr_t fb_len;
+ hwaddr fb_len;
void *mesh;
- target_phys_addr_t mesh_len;
+ hwaddr mesh_len;
float m;
trace_milkymist_tmu2_start();
@@ -310,7 +310,7 @@
qemu_irq_pulse(s->irq);
}
-static uint64_t tmu2_read(void *opaque, target_phys_addr_t addr,
+static uint64_t tmu2_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistTMU2State *s = opaque;
@@ -372,7 +372,7 @@
}
}
-static void tmu2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void tmu2_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistTMU2State *s = opaque;
diff --git a/hw/milkymist-uart.c b/hw/milkymist-uart.c
index 291fe3c..aefa8c7 100644
--- a/hw/milkymist-uart.c
+++ b/hw/milkymist-uart.c
@@ -78,7 +78,7 @@
}
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistUartState *s = opaque;
@@ -107,7 +107,7 @@
return r;
}
-static void uart_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void uart_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistUartState *s = opaque;
diff --git a/hw/milkymist-vgafb.c b/hw/milkymist-vgafb.c
index cd4365d..8d36bc1 100644
--- a/hw/milkymist-vgafb.c
+++ b/hw/milkymist-vgafb.c
@@ -155,7 +155,7 @@
s->invalidate = 1;
}
-static uint64_t vgafb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vgafb_read(void *opaque, hwaddr addr,
unsigned size)
{
MilkymistVgafbState *s = opaque;
@@ -193,7 +193,7 @@
return r;
}
-static void vgafb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void vgafb_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
MilkymistVgafbState *s = opaque;
diff --git a/hw/milkymist.c b/hw/milkymist.c
index ca9ed43..4c8111a 100644
--- a/hw/milkymist.c
+++ b/hw/milkymist.c
@@ -38,11 +38,11 @@
typedef struct {
LM32CPU *cpu;
- target_phys_addr_t bootstrap_pc;
- target_phys_addr_t flash_base;
- target_phys_addr_t initrd_base;
+ hwaddr bootstrap_pc;
+ hwaddr flash_base;
+ hwaddr initrd_base;
size_t initrd_size;
- target_phys_addr_t cmdline_base;
+ hwaddr cmdline_base;
} ResetInfo;
static void cpu_irq_handler(void *opaque, int irq, int level)
@@ -91,14 +91,14 @@
ResetInfo *reset_info;
/* memory map */
- target_phys_addr_t flash_base = 0x00000000;
+ hwaddr flash_base = 0x00000000;
size_t flash_sector_size = 128 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t sdram_base = 0x40000000;
+ hwaddr sdram_base = 0x40000000;
size_t sdram_size = 128 * 1024 * 1024;
- target_phys_addr_t initrd_base = sdram_base + 0x1002000;
- target_phys_addr_t cmdline_base = sdram_base + 0x1000000;
+ hwaddr initrd_base = sdram_base + 0x1002000;
+ hwaddr cmdline_base = sdram_base + 0x1000000;
size_t initrd_max = sdram_size - 0x1002000;
reset_info = g_malloc0(sizeof(ResetInfo));
diff --git a/hw/mips.h b/hw/mips.h
index a7e6d4c..f7e9b7e 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -12,7 +12,7 @@
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
+void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
@@ -21,9 +21,9 @@
MemoryRegion *sysmem);
/* dp8393x.c */
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write));
#endif
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 6bd231d..0847427 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -56,12 +56,12 @@
cpu_reset(CPU(cpu));
}
-static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
{
return cpu_inw(0x71);
}
-static void rtc_write(void *opaque, target_phys_addr_t addr,
+static void rtc_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
cpu_outw(0x71, val & 0xff);
@@ -73,7 +73,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
unsigned size)
{
/* Nothing to do. That is only to ensure that
@@ -81,7 +81,7 @@
return 0xff;
}
-static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
+static void dma_dummy_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
/* Nothing to do. That is only to ensure that
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 22ec8b9..0571d58 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -231,7 +231,7 @@
eeprom.sda = sda;
}
-static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
+static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
unsigned size)
{
MaltaFPGAState *s = opaque;
@@ -319,7 +319,7 @@
return val;
}
-static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
+static void malta_fpga_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MaltaFPGAState *s = opaque;
@@ -441,7 +441,7 @@
}
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
- target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
+ hwaddr base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 539577b..325098a 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -44,7 +44,7 @@
const char *initrd_filename;
} loaderparams;
-static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
+static void mips_qemu_write (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
@@ -53,7 +53,7 @@
qemu_system_shutdown_request ();
}
-static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr,
+static uint64_t mips_qemu_read (void *opaque, hwaddr addr,
unsigned size)
{
return 0;
diff --git a/hw/mipsnet.c b/hw/mipsnet.c
index 28063b1..bece332 100644
--- a/hw/mipsnet.c
+++ b/hw/mipsnet.c
@@ -96,7 +96,7 @@
return size;
}
-static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
unsigned int size)
{
MIPSnetState *s = opaque;
@@ -142,7 +142,7 @@
return ret;
}
-static void mipsnet_ioport_write(void *opaque, target_phys_addr_t addr,
+static void mipsnet_ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
MIPSnetState *s = opaque;
diff --git a/hw/mpc8544_guts.c b/hw/mpc8544_guts.c
index 13b0ddd..873cb8c 100644
--- a/hw/mpc8544_guts.c
+++ b/hw/mpc8544_guts.c
@@ -58,7 +58,7 @@
typedef struct GutsState GutsState;
-static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t value = 0;
@@ -80,7 +80,7 @@
return value;
}
-static void mpc8544_guts_write(void *opaque, target_phys_addr_t addr,
+static void mpc8544_guts_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
diff --git a/hw/msix.c b/hw/msix.c
index b623cb5..136ef09 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -157,7 +157,7 @@
}
}
-static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIDevice *dev = opaque;
@@ -165,7 +165,7 @@
return pci_get_long(dev->msix_table + addr);
}
-static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
+static void msix_table_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIDevice *dev = opaque;
@@ -188,7 +188,7 @@
},
};
-static uint64_t msix_pba_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIDevice *dev = opaque;
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 024192d..fb4b739 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -91,7 +91,7 @@
static uint64_t
-mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
+mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
@@ -128,7 +128,7 @@
}
static void
-mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
+mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
diff --git a/hw/multiboot.c b/hw/multiboot.c
index b1e04c5..09ec5b2 100644
--- a/hw/multiboot.c
+++ b/hw/multiboot.c
@@ -80,15 +80,15 @@
/* buffer holding kernel, cmdlines and mb_infos */
void *mb_buf;
/* address in target */
- target_phys_addr_t mb_buf_phys;
+ hwaddr mb_buf_phys;
/* size of mb_buf in bytes */
unsigned mb_buf_size;
/* offset of mb-info's in bytes */
- target_phys_addr_t offset_mbinfo;
+ hwaddr offset_mbinfo;
/* offset in buffer for cmdlines in bytes */
- target_phys_addr_t offset_cmdlines;
+ hwaddr offset_cmdlines;
/* offset of modules in bytes */
- target_phys_addr_t offset_mods;
+ hwaddr offset_mods;
/* available slots for mb modules infos */
int mb_mods_avail;
/* currently used slots of mb modules */
@@ -97,7 +97,7 @@
static uint32_t mb_add_cmdline(MultibootState *s, const char *cmdline)
{
- target_phys_addr_t p = s->offset_cmdlines;
+ hwaddr p = s->offset_cmdlines;
char *b = (char *)s->mb_buf + p;
get_opt_value(b, strlen(cmdline) + 1, cmdline);
@@ -106,8 +106,8 @@
}
static void mb_add_mod(MultibootState *s,
- target_phys_addr_t start, target_phys_addr_t end,
- target_phys_addr_t cmdline_phys)
+ hwaddr start, hwaddr end,
+ hwaddr cmdline_phys)
{
char *p;
assert(s->mb_mods_count < s->mb_mods_avail);
@@ -276,7 +276,7 @@
*next_initrd = '\0';
/* if a space comes after the module filename, treat everything
after that as parameters */
- target_phys_addr_t c = mb_add_cmdline(&mbs, initrd_filename);
+ hwaddr c = mb_add_cmdline(&mbs, initrd_filename);
if ((next_space = strchr(initrd_filename, ' ')))
*next_space = '\0';
mb_debug("multiboot loading module: %s\n", initrd_filename);
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 159d3c3..beec76b 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -266,7 +266,7 @@
} while (desc_addr != s->tx_queue[queue_index]);
}
-static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -308,7 +308,7 @@
}
}
-static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_eth_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -540,7 +540,7 @@
s->brightness |= level << irq;
}
-static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset,
unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -554,7 +554,7 @@
}
}
-static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_lcd_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -682,7 +682,7 @@
mv88w8618_pic_update(s);
}
-static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -696,7 +696,7 @@
}
}
-static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_pic_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -815,7 +815,7 @@
s->ptimer = ptimer_init(bh);
}
-static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset,
unsigned size)
{
mv88w8618_pit_state *s = opaque;
@@ -831,7 +831,7 @@
}
}
-static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_pit_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_pit_state *s = opaque;
@@ -957,7 +957,7 @@
} mv88w8618_flashcfg_state;
static uint64_t mv88w8618_flashcfg_read(void *opaque,
- target_phys_addr_t offset,
+ hwaddr offset,
unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -971,7 +971,7 @@
}
}
-static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -1032,7 +1032,7 @@
#define MP_BOARD_REVISION 0x31
-static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_misc_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (offset) {
@@ -1044,7 +1044,7 @@
}
}
-static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_misc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
}
@@ -1068,7 +1068,7 @@
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
-static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset,
unsigned size)
{
switch (offset) {
@@ -1084,7 +1084,7 @@
}
}
-static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_wlan_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
}
@@ -1202,7 +1202,7 @@
}
}
-static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
musicpal_gpio_state *s = opaque;
@@ -1241,7 +1241,7 @@
}
}
-static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
musicpal_gpio_state *s = opaque;
diff --git a/hw/ne2000.c b/hw/ne2000.c
index 15605c4..d3dd9a6 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -652,7 +652,7 @@
}
};
-static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ne2000_read(void *opaque, hwaddr addr,
unsigned size)
{
NE2000State *s = opaque;
@@ -671,7 +671,7 @@
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void ne2000_write(void *opaque, target_phys_addr_t addr,
+static void ne2000_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
NE2000State *s = opaque;
diff --git a/hw/nvram.h b/hw/nvram.h
index 8924da4..a4a1db4 100644
--- a/hw/nvram.h
+++ b/hw/nvram.h
@@ -36,7 +36,7 @@
void m48t59_toggle_lock (void *private, int lock);
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int type);
-M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int type);
void m48t59_set_addr (void *opaque, uint32_t addr);
diff --git a/hw/omap.h b/hw/omap.h
index 413851b..8bd7c73 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -65,7 +65,7 @@
/* OMAP2 l4 Interconnect */
struct omap_l4_s;
struct omap_l4_region_s {
- target_phys_addr_t offset;
+ hwaddr offset;
size_t size;
int access;
};
@@ -80,13 +80,13 @@
struct omap_l4_s *bus;
int regions;
const struct omap_l4_region_s *start;
- target_phys_addr_t base;
+ hwaddr base;
uint32_t component;
uint32_t control;
uint32_t status;
};
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
- target_phys_addr_t base, int ta_num);
+ hwaddr base, int ta_num);
struct omap_target_agent_s;
struct omap_target_agent_s *omap_l4ta_get(
@@ -94,23 +94,23 @@
const struct omap_l4_region_s *regions,
const struct omap_l4_agent_info_s *agents,
int cs);
-target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
+hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr);
-target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
int region);
-target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
int region);
/* OMAP2 SDRAM controller */
struct omap_sdrc_s;
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
- target_phys_addr_t base);
+ hwaddr base);
void omap_sdrc_reset(struct omap_sdrc_s *s);
/* OMAP2 general purpose memory controller */
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq drq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
@@ -433,11 +433,11 @@
};
struct soc_dma_s;
-struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
-struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
@@ -469,10 +469,10 @@
/* Only used in OMAP DMA 3.x gigacells */
struct omap_dma_lcd_channel_s {
enum omap_dma_port src;
- target_phys_addr_t src_f1_top;
- target_phys_addr_t src_f1_bottom;
- target_phys_addr_t src_f2_top;
- target_phys_addr_t src_f2_bottom;
+ hwaddr src_f1_top;
+ hwaddr src_f1_bottom;
+ hwaddr src_f2_top;
+ hwaddr src_f2_bottom;
/* Used in OMAP DMA 3.2 gigacell */
unsigned char brust_f1;
@@ -508,7 +508,7 @@
int dual;
int current_frame;
- target_phys_addr_t phys_framebuffer[2];
+ hwaddr phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct soc_dma_s *s);
@@ -659,7 +659,7 @@
void omap_synctimer_reset(struct omap_synctimer_s *s);
struct omap_uart_s;
-struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
+struct omap_uart_s *omap_uart_init(hwaddr base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr);
@@ -728,7 +728,7 @@
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk);
@@ -744,7 +744,7 @@
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t l3_base,
+ hwaddr l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2);
@@ -752,7 +752,7 @@
/* omap_mmc.c */
struct omap_mmc_s;
-struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+struct omap_mmc_s *omap_mmc_init(hwaddr base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk);
@@ -829,11 +829,11 @@
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
- target_phys_addr_t offset);
+ hwaddr offset);
void (*write[3])(struct omap_mpu_state_s *s,
- target_phys_addr_t offset, uint32_t value);
+ hwaddr offset, uint32_t value);
int (*addr_valid)(struct omap_mpu_state_s *s,
- target_phys_addr_t addr);
+ hwaddr addr);
} port[__omap_dma_port_last];
unsigned long sdram_size;
@@ -942,16 +942,16 @@
unsigned long sdram_size,
const char *core);
-#define OMAP_FMT_plx "%#08" TARGET_PRIxPHYS
+#define OMAP_FMT_plx "%#08" HWADDR_PRIx
-uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
+void omap_badwidth_write8(void *opaque, hwaddr addr,
uint32_t value);
-uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
+void omap_badwidth_write16(void *opaque, hwaddr addr,
uint32_t value);
-uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
+void omap_badwidth_write32(void *opaque, hwaddr addr,
uint32_t value);
void omap_mpu_wakeup(void *opaque, int irq, int req);
diff --git a/hw/omap1.c b/hw/omap1.c
index ad60cc4..4d5815e 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -26,7 +26,7 @@
#include "sysbus.h"
/* Should signal the TCMI/GPMC */
-uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
{
uint8_t ret;
@@ -35,7 +35,7 @@
return ret;
}
-void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write8(void *opaque, hwaddr addr,
uint32_t value)
{
uint8_t val8 = value;
@@ -44,7 +44,7 @@
cpu_physical_memory_write(addr, (void *) &val8, 1);
}
-uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
{
uint16_t ret;
@@ -53,7 +53,7 @@
return ret;
}
-void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write16(void *opaque, hwaddr addr,
uint32_t value)
{
uint16_t val16 = value;
@@ -62,7 +62,7 @@
cpu_physical_memory_write(addr, (void *) &val16, 2);
}
-uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -71,7 +71,7 @@
return ret;
}
-void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write32(void *opaque, hwaddr addr,
uint32_t value)
{
OMAP_32B_REG(addr);
@@ -176,7 +176,7 @@
timer->rate = omap_clk_getrate(timer->clk);
}
-static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@@ -200,7 +200,7 @@
return 0;
}
-static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpu_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@@ -251,7 +251,7 @@
}
static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
@@ -282,7 +282,7 @@
int reset;
};
-static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@@ -307,7 +307,7 @@
return 0;
}
-static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_wd_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@@ -380,7 +380,7 @@
}
static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
@@ -405,7 +405,7 @@
MemoryRegion iomem;
};
-static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
@@ -432,7 +432,7 @@
return 0;
}
-static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_os_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
@@ -486,7 +486,7 @@
}
static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
@@ -506,7 +506,7 @@
}
/* Ultra Low-Power Device Module */
-static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -573,7 +573,7 @@
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
}
-static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
+static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -726,7 +726,7 @@
}
static void omap_ulpd_pm_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
@@ -736,7 +736,7 @@
}
/* OMAP Pin Configuration */
-static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -843,7 +843,7 @@
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
}
-static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
+static void omap_pin_cfg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -944,7 +944,7 @@
}
static void omap_pin_cfg_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
@@ -954,7 +954,7 @@
}
/* Device Identification, Die Identification */
-static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_id_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1001,7 +1001,7 @@
return 0;
}
-static void omap_id_write(void *opaque, target_phys_addr_t addr,
+static void omap_id_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
@@ -1035,7 +1035,7 @@
}
/* MPUI Control (Dummy) */
-static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1068,7 +1068,7 @@
return 0;
}
-static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1109,7 +1109,7 @@
s->mpui_ctrl = 0x0003ff1b;
}
-static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
@@ -1131,7 +1131,7 @@
uint16_t enh_control;
};
-static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@@ -1161,7 +1161,7 @@
return 0;
}
-static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
+static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@@ -1215,7 +1215,7 @@
}
static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
- MemoryRegion *memory, target_phys_addr_t base,
+ MemoryRegion *memory, hwaddr base,
qemu_irq abort_irq, omap_clk clk)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
@@ -1232,7 +1232,7 @@
}
/* Dummy Traffic Controller's Memory Interface */
-static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1270,7 +1270,7 @@
return 0;
}
-static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
+static void omap_tcmi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1330,7 +1330,7 @@
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
@@ -1346,7 +1346,7 @@
omap_clk dpll;
};
-static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@@ -1362,7 +1362,7 @@
return 0;
}
-static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
+static void omap_dpll_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@@ -1412,7 +1412,7 @@
}
static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
- target_phys_addr_t base, omap_clk clk)
+ hwaddr base, omap_clk clk)
{
struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
@@ -1425,7 +1425,7 @@
}
/* MPU Clock/Reset/Power Mode Control */
-static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1627,7 +1627,7 @@
}
}
-static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1714,7 +1714,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1758,7 +1758,7 @@
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
}
-static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkdsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1823,8 +1823,8 @@
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
- target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
+static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
+ hwaddr dsp_base, struct omap_mpu_state_s *s)
{
memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
"omap-clkm", 0x100);
@@ -1903,7 +1903,7 @@
s->row_latch = ~rows;
}
-static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
@@ -1963,7 +1963,7 @@
return 0;
}
-static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpuio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
@@ -2072,7 +2072,7 @@
}
static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
@@ -2159,7 +2159,7 @@
}
}
-static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
@@ -2193,7 +2193,7 @@
return 0;
}
-static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
+static void omap_uwire_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
@@ -2263,7 +2263,7 @@
}
static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq dma,
omap_clk clk)
@@ -2312,7 +2312,7 @@
}
}
-static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
@@ -2332,7 +2332,7 @@
return 0;
}
-static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
@@ -2381,7 +2381,7 @@
}
static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
omap_clk clk)
{
struct omap_pwl_s *s = g_malloc0(sizeof(*s));
@@ -2405,7 +2405,7 @@
omap_clk clk;
};
-static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
@@ -2427,7 +2427,7 @@
return 0;
}
-static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
@@ -2488,7 +2488,7 @@
}
static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
omap_clk clk)
{
struct omap_pwt_s *s = g_malloc0(sizeof(*s));
@@ -2536,7 +2536,7 @@
printf("%s: conversion failed\n", __FUNCTION__);
}
-static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
@@ -2618,7 +2618,7 @@
return 0;
}
-static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
+static void omap_rtc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
@@ -2901,7 +2901,7 @@
}
static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq timerirq, qemu_irq alarmirq,
omap_clk clk)
{
@@ -3129,7 +3129,7 @@
omap_mcbsp_rx_stop(s);
}
-static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -3227,7 +3227,7 @@
return 0;
}
-static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -3365,7 +3365,7 @@
OMAP_BAD_REG(addr);
}
-static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writew(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -3396,7 +3396,7 @@
omap_badwidth_write16(opaque, addr, value);
}
-static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
@@ -3432,7 +3432,7 @@
}
static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq *dma, omap_clk clk)
{
@@ -3547,7 +3547,7 @@
omap_lpg_update(s);
}
-static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
@@ -3569,7 +3569,7 @@
return 0;
}
-static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
+static void omap_lpg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
@@ -3613,7 +3613,7 @@
}
static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
- target_phys_addr_t base, omap_clk clk)
+ hwaddr base, omap_clk clk)
{
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
@@ -3631,7 +3631,7 @@
}
/* MPUI Peripheral Bridge configuration */
-static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
unsigned size)
{
if (size != 2) {
@@ -3645,7 +3645,7 @@
return 0;
}
-static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_io_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
/* FIXME: infinite loop */
@@ -3706,8 +3706,8 @@
}
static const struct omap_map_s {
- target_phys_addr_t phys_dsp;
- target_phys_addr_t phys_mpu;
+ hwaddr phys_dsp;
+ hwaddr phys_mpu;
uint32_t size;
const char *name;
} omap15xx_dsp_mm[] = {
@@ -3778,38 +3778,38 @@
/* DMA ports for OMAP1 */
static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
}
static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
addr);
}
static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
}
static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
}
static int omap_validate_local_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
}
static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
diff --git a/hw/omap2.c b/hw/omap2.c
index 4278dd1..96aba71 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -324,7 +324,7 @@
omap_eac_interrupt_update(s);
}
-static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_eac_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
@@ -440,7 +440,7 @@
return 0;
}
-static void omap_eac_write(void *opaque, target_phys_addr_t addr,
+static void omap_eac_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
@@ -644,7 +644,7 @@
omap_sti_interrupt_update(s);
}
-static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sti_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -685,7 +685,7 @@
return 0;
}
-static void omap_sti_write(void *opaque, target_phys_addr_t addr,
+static void omap_sti_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -741,14 +741,14 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
}
-static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
+static void omap_sti_fifo_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -780,7 +780,7 @@
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
+ hwaddr channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
struct omap_sti_s *s = (struct omap_sti_s *)
@@ -1040,7 +1040,7 @@
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
}
-static uint64_t omap_prcm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
@@ -1352,7 +1352,7 @@
}
}
-static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
+static void omap_prcm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
@@ -1832,7 +1832,7 @@
uint32_t msuspendmux[5];
};
-static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -1857,7 +1857,7 @@
return 0;
}
-static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -1957,7 +1957,7 @@
return 0;
}
-static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write8(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -1981,7 +1981,7 @@
}
}
-static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -2226,7 +2226,7 @@
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return 1;
}
diff --git a/hw/omap_dma.c b/hw/omap_dma.c
index 389cb78..e619c7b 100644
--- a/hw/omap_dma.c
+++ b/hw/omap_dma.c
@@ -31,7 +31,7 @@
int endian_lock[2];
int translate[2];
enum omap_dma_port port[2];
- target_phys_addr_t addr[2];
+ hwaddr addr[2];
omap_dma_addressing_t mode[2];
uint32_t elements;
uint16_t frames;
@@ -78,7 +78,7 @@
struct omap_dma_channel_s *sibling;
struct omap_dma_reg_set_s {
- target_phys_addr_t src, dest;
+ hwaddr src, dest;
int frame;
int element;
int pck_element;
@@ -914,7 +914,7 @@
break;
case 0x06: /* SYS_DMA_CSR_CH0 */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((hwaddr) reg);
break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
@@ -954,7 +954,7 @@
break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((hwaddr) reg);
break;
case 0x1c: /* DMA_CDEI */
@@ -1446,7 +1446,7 @@
return 0;
}
-static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dma_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1494,7 +1494,7 @@
return 0;
}
-static void omap_dma_write(void *opaque, target_phys_addr_t addr,
+static void omap_dma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1618,7 +1618,7 @@
}
}
-struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
@@ -1692,7 +1692,7 @@
qemu_irq_raise(s->irq[3]);
}
-static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1842,7 +1842,7 @@
}
}
-static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
+static void omap_dma4_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1988,12 +1988,12 @@
break;
case 0x1c: /* DMA4_CSSA */
- ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[0] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
- ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[1] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
@@ -2040,7 +2040,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)
diff --git a/hw/omap_dss.c b/hw/omap_dss.c
index 86ed6ea..1e83726 100644
--- a/hw/omap_dss.c
+++ b/hw/omap_dss.c
@@ -60,7 +60,7 @@
int nx;
int ny;
- target_phys_addr_t addr[3];
+ hwaddr addr[3];
uint32_t attr;
uint32_t tresh;
@@ -168,7 +168,7 @@
omap_dispc_interrupt_update(s);
}
-static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_diss_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -206,7 +206,7 @@
return 0;
}
-static void omap_diss_write(void *opaque, target_phys_addr_t addr,
+static void omap_diss_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -246,7 +246,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_disc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -371,7 +371,7 @@
return 0;
}
-static void omap_disc_write(void *opaque, target_phys_addr_t addr,
+static void omap_disc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -502,11 +502,11 @@
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
- s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[0] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
- s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[1] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
@@ -543,7 +543,7 @@
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
- s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[2] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
@@ -602,11 +602,11 @@
static void omap_rfbi_transfer_start(struct omap_dss_s *s)
{
void *data;
- target_phys_addr_t len;
- target_phys_addr_t data_addr;
+ hwaddr len;
+ hwaddr data_addr;
int pitch;
static void *bounce_buffer;
- static target_phys_addr_t bounce_len;
+ static hwaddr bounce_len;
if (!s->rfbi.enable || s->rfbi.busy)
return;
@@ -663,7 +663,7 @@
omap_dispc_interrupt_update(s);
}
-static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -730,7 +730,7 @@
return 0;
}
-static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
+static void omap_rfbi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -864,7 +864,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_venc_read(void *opaque, hwaddr addr,
unsigned size)
{
if (size != 4) {
@@ -924,7 +924,7 @@
return 0;
}
-static void omap_venc_write(void *opaque, target_phys_addr_t addr,
+static void omap_venc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
@@ -986,7 +986,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_im3_read(void *opaque, hwaddr addr,
unsigned size)
{
if (size != 4) {
@@ -1012,7 +1012,7 @@
return 0;
}
-static void omap_im3_write(void *opaque, target_phys_addr_t addr,
+static void omap_im3_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
@@ -1041,7 +1041,7 @@
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t l3_base,
+ hwaddr l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
diff --git a/hw/omap_gpio.c b/hw/omap_gpio.c
index 201ff77..2565532 100644
--- a/hw/omap_gpio.c
+++ b/hw/omap_gpio.c
@@ -61,7 +61,7 @@
}
}
-static uint64_t omap_gpio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
@@ -99,7 +99,7 @@
return 0;
}
-static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
@@ -300,7 +300,7 @@
s->delay = 0;
}
-static uint32_t omap2_gpio_module_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@@ -372,7 +372,7 @@
return 0;
}
-static void omap2_gpio_module_write(void *opaque, target_phys_addr_t addr,
+static void omap2_gpio_module_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@@ -514,12 +514,12 @@
}
}
-static uint32_t omap2_gpio_module_readp(void *opaque, target_phys_addr_t addr)
+static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
{
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
}
-static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr,
+static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
uint32_t value)
{
uint32_t cur = 0;
@@ -604,7 +604,7 @@
s->gpo = 0;
}
-static uint64_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
@@ -633,7 +633,7 @@
return 0;
}
-static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
+static void omap2_gpif_top_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 2fc4137..1f7c5bc 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -121,7 +121,7 @@
* all addresses in the region behave like accesses to the relevant
* GPMC_NAND_DATA_i register (which is actually implemented to call these)
*/
-static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_nand_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
@@ -200,7 +200,7 @@
}
}
-static void omap_nand_write(void *opaque, target_phys_addr_t addr,
+static void omap_nand_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
@@ -281,7 +281,7 @@
* engine is enabled -- all addresses in the region behave alike:
* data is read or written to the FIFO.
*/
-static uint64_t omap_gpmc_prefetch_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -311,7 +311,7 @@
return data;
}
-static void omap_gpmc_prefetch_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -484,7 +484,7 @@
ecc_reset(&s->ecc[i]);
}
-static int gpmc_wordaccess_only(target_phys_addr_t addr)
+static int gpmc_wordaccess_only(hwaddr addr)
{
/* Return true if the register offset is to a register that
* only permits word width accesses.
@@ -502,7 +502,7 @@
return 1;
}
-static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -614,7 +614,7 @@
return 0;
}
-static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpmc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -819,7 +819,7 @@
};
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq drq)
{
int cs;
diff --git a/hw/omap_gptimer.c b/hw/omap_gptimer.c
index 7a14519..e39da74 100644
--- a/hw/omap_gptimer.c
+++ b/hw/omap_gptimer.c
@@ -258,7 +258,7 @@
omap_gp_timer_update(s);
}
-static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@@ -324,7 +324,7 @@
return 0;
}
-static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
uint32_t ret;
@@ -338,7 +338,7 @@
}
}
-static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_gp_timer_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@@ -438,7 +438,7 @@
}
}
-static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
+static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
index 20bc82e..ba08e64 100644
--- a/hw/omap_i2c.c
+++ b/hw/omap_i2c.c
@@ -149,7 +149,7 @@
s->test = 0;
}
-static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
{
OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -248,7 +248,7 @@
return 0;
}
-static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
+static void omap_i2c_write(void *opaque, hwaddr addr,
uint32_t value)
{
OMAPI2CState *s = opaque;
@@ -390,7 +390,7 @@
}
}
-static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
+static void omap_i2c_writeb(void *opaque, hwaddr addr,
uint32_t value)
{
OMAPI2CState *s = opaque;
diff --git a/hw/omap_intc.c b/hw/omap_intc.c
index 5076e07..61e0daf 100644
--- a/hw/omap_intc.c
+++ b/hw/omap_intc.c
@@ -145,7 +145,7 @@
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
-static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -223,7 +223,7 @@
return 0;
}
-static void omap_inth_write(void *opaque, target_phys_addr_t addr,
+static void omap_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -396,7 +396,7 @@
.class_init = omap_intc_class_init,
};
-static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -477,7 +477,7 @@
return 0;
}
-static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
+static void omap2_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
diff --git a/hw/omap_l4.c b/hw/omap_l4.c
index dbad7f6..09e983f 100644
--- a/hw/omap_l4.c
+++ b/hw/omap_l4.c
@@ -22,13 +22,13 @@
struct omap_l4_s {
MemoryRegion *address_space;
- target_phys_addr_t base;
+ hwaddr base;
int ta_num;
struct omap_target_agent_s ta[0];
};
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
- target_phys_addr_t base, int ta_num)
+ hwaddr base, int ta_num)
{
struct omap_l4_s *bus = g_malloc0(
sizeof(*bus) + ta_num * sizeof(*bus->ta));
@@ -40,19 +40,19 @@
return bus;
}
-target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
int region)
{
return ta->bus->base + ta->start[region].offset;
}
-target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
+hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
int region)
{
return ta->start[region].size;
}
-static uint64_t omap_l4ta_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@@ -76,7 +76,7 @@
return 0;
}
-static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
+static void omap_l4ta_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@@ -143,10 +143,10 @@
return ta;
}
-target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
+hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr)
{
- target_phys_addr_t base;
+ hwaddr base;
if (region < 0 || region >= ta->regions) {
fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
index e2ba108..bf177c2 100644
--- a/hw/omap_lcdc.c
+++ b/hw/omap_lcdc.c
@@ -117,7 +117,7 @@
draw_line_func draw_line;
int size, height, first, last;
int width, linesize, step, bpp, frame_offset;
- target_phys_addr_t frame_base;
+ hwaddr frame_base;
if (!omap_lcd || omap_lcd->plm == 1 ||
!omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
@@ -359,7 +359,7 @@
}
}
-static uint64_t omap_lcdc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -392,7 +392,7 @@
return 0;
}
-static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
+static void omap_lcdc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -465,7 +465,7 @@
}
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk)
diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c
index aec0285..7ecd9bd 100644
--- a/hw/omap_mmc.c
+++ b/hw/omap_mmc.c
@@ -306,7 +306,7 @@
host->clkdiv = 0;
}
-static uint64_t omap_mmc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
unsigned size)
{
uint16_t i;
@@ -399,7 +399,7 @@
return 0;
}
-static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
+static void omap_mmc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
int i;
@@ -572,7 +572,7 @@
}
}
-struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+struct omap_mmc_s *omap_mmc_init(hwaddr base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
diff --git a/hw/omap_sdrc.c b/hw/omap_sdrc.c
index 784e326..b0f3b8e 100644
--- a/hw/omap_sdrc.c
+++ b/hw/omap_sdrc.c
@@ -31,7 +31,7 @@
s->config = 0x10;
}
-static uint64_t omap_sdrc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@@ -86,7 +86,7 @@
return 0;
}
-static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
+static void omap_sdrc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@@ -154,7 +154,7 @@
};
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
- target_phys_addr_t base)
+ hwaddr base)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *)
g_malloc0(sizeof(struct omap_sdrc_s));
diff --git a/hw/omap_spi.c b/hw/omap_spi.c
index 8f2b697..42d5149 100644
--- a/hw/omap_spi.c
+++ b/hw/omap_spi.c
@@ -130,7 +130,7 @@
omap_mcspi_interrupt_update(s);
}
-static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
@@ -204,7 +204,7 @@
return 0;
}
-static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcspi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index ad17487..eb2bf05 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -59,7 +59,7 @@
* - 1 RTC
*/
-static uint64_t static_read(void *opaque, target_phys_addr_t offset,
+static uint64_t static_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t *val = (uint32_t *) opaque;
@@ -68,7 +68,7 @@
return *val >> ((offset & mask) << 3);
}
-static void static_write(void *opaque, target_phys_addr_t offset,
+static void static_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
#ifdef SPY
diff --git a/hw/omap_synctimer.c b/hw/omap_synctimer.c
index 367f26e..7031a88 100644
--- a/hw/omap_synctimer.c
+++ b/hw/omap_synctimer.c
@@ -36,7 +36,7 @@
s->val = omap_synctimer_read(s);
}
-static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
@@ -52,7 +52,7 @@
return 0;
}
-static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
uint32_t ret;
@@ -66,7 +66,7 @@
}
}
-static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
+static void omap_synctimer_write(void *opaque, hwaddr addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
diff --git a/hw/omap_tap.c b/hw/omap_tap.c
index 0277c73..e273e97 100644
--- a/hw/omap_tap.c
+++ b/hw/omap_tap.c
@@ -22,7 +22,7 @@
#include "omap.h"
/* TEST-Chip-level TAP */
-static uint64_t omap_tap_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tap_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -91,7 +91,7 @@
return 0;
}
-static void omap_tap_write(void *opaque, target_phys_addr_t addr,
+static void omap_tap_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
diff --git a/hw/omap_uart.c b/hw/omap_uart.c
index 1c16a54..92f2702 100644
--- a/hw/omap_uart.c
+++ b/hw/omap_uart.c
@@ -26,7 +26,7 @@
/* UARTs */
struct omap_uart_s {
MemoryRegion iomem;
- target_phys_addr_t base;
+ hwaddr base;
SerialState *serial; /* TODO */
struct omap_target_agent_s *ta;
omap_clk fclk;
@@ -50,7 +50,7 @@
s->clksel = 0;
}
-struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
+struct omap_uart_s *omap_uart_init(hwaddr base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
@@ -68,7 +68,7 @@
return s;
}
-static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_uart_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@@ -106,7 +106,7 @@
return 0;
}
-static void omap_uart_write(void *opaque, target_phys_addr_t addr,
+static void omap_uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@@ -164,7 +164,7 @@
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
{
- target_phys_addr_t base = omap_l4_attach(ta, 0, NULL);
+ hwaddr base = omap_l4_attach(ta, 0, NULL);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr);
diff --git a/hw/onenand.c b/hw/onenand.c
index 0f7b755..1803e4c 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -42,7 +42,7 @@
uint16_t ver;
} id;
int shift;
- target_phys_addr_t base;
+ hwaddr base;
qemu_irq intr;
qemu_irq rdy;
BlockDriverState *bdrv;
@@ -588,7 +588,7 @@
onenand_intr_update(s);
}
-static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
+static uint64_t onenand_read(void *opaque, hwaddr addr,
unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
@@ -653,7 +653,7 @@
return 0;
}
-static void onenand_write(void *opaque, target_phys_addr_t addr,
+static void onenand_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
@@ -760,7 +760,7 @@
OneNANDState *s = (OneNANDState *)dev;
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
void *ram;
- s->base = (target_phys_addr_t)-1;
+ s->base = (hwaddr)-1;
s->rdy = NULL;
s->blocks = size >> BLOCK_SHIFT;
s->secs = size >> 9;
diff --git a/hw/opencores_eth.c b/hw/opencores_eth.c
index 8c15969..b2780b9 100644
--- a/hw/opencores_eth.c
+++ b/hw/opencores_eth.c
@@ -528,7 +528,7 @@
}
static uint64_t open_eth_reg_read(void *opaque,
- target_phys_addr_t addr, unsigned int size)
+ hwaddr addr, unsigned int size)
{
static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
};
@@ -620,7 +620,7 @@
}
static void open_eth_reg_write(void *opaque,
- target_phys_addr_t addr, uint64_t val, unsigned int size)
+ hwaddr addr, uint64_t val, unsigned int size)
{
static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
[MODER] = open_eth_moder_host_write,
@@ -644,7 +644,7 @@
}
static uint64_t open_eth_desc_read(void *opaque,
- target_phys_addr_t addr, unsigned int size)
+ hwaddr addr, unsigned int size)
{
OpenEthState *s = opaque;
uint64_t v = 0;
@@ -656,7 +656,7 @@
}
static void open_eth_desc_write(void *opaque,
- target_phys_addr_t addr, uint64_t val, unsigned int size)
+ hwaddr addr, uint64_t val, unsigned int size)
{
OpenEthState *s = opaque;
diff --git a/hw/openpic.c b/hw/openpic.c
index b9d8568..8b3784a 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -178,9 +178,9 @@
return cpu_single_env->cpu_index;
}
-static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
+static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
int idx);
-static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx);
enum {
@@ -596,7 +596,7 @@
#endif
#endif /* 0 : Code provision for Intel model */
-static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
{
openpic_t *opp = opaque;
IRQ_dst_t *dst;
@@ -662,7 +662,7 @@
}
}
-static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -826,7 +826,7 @@
return retval;
}
-static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx)
{
openpic_t *opp = opaque;
@@ -886,12 +886,12 @@
}
}
-static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
{
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
}
-static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
+static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
int idx)
{
openpic_t *opp = opaque;
@@ -970,18 +970,18 @@
return retval;
}
-static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
{
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
}
static void openpic_buggy_write (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
printf("Invalid OPENPIC write access !\n");
}
-static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
{
printf("Invalid OPENPIC read access !\n");
@@ -989,7 +989,7 @@
}
static void openpic_writel (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ hwaddr addr, uint32_t val)
{
openpic_t *opp = opaque;
@@ -1010,7 +1010,7 @@
}
}
-static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
+static uint32_t openpic_readl (void *opaque,hwaddr addr)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -1034,7 +1034,7 @@
return retval;
}
-static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
+static uint64_t openpic_read(void *opaque, hwaddr addr,
unsigned size)
{
openpic_t *opp = opaque;
@@ -1045,7 +1045,7 @@
}
}
-static void openpic_write(void *opaque, target_phys_addr_t addr,
+static void openpic_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
openpic_t *opp = opaque;
@@ -1300,7 +1300,7 @@
mpp->glbc = 0x00000000;
}
-static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
{
openpic_t *mpp = opaque;
int idx, cpu;
@@ -1333,7 +1333,7 @@
}
}
-static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1368,7 +1368,7 @@
return retval;
}
-static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_ext_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1390,7 +1390,7 @@
}
}
-static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_ext_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1416,7 +1416,7 @@
return retval;
}
-static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_int_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1438,7 +1438,7 @@
}
}
-static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_int_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1464,7 +1464,7 @@
return retval;
}
-static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_msg_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1486,7 +1486,7 @@
}
}
-static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_msg_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1512,7 +1512,7 @@
return retval;
}
-static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_msi_write (void *opaque, hwaddr addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1533,7 +1533,7 @@
}
}
}
-static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_msi_read (void *opaque, hwaddr addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1657,7 +1657,7 @@
.endianness = DEVICE_BIG_ENDIAN,
};
-qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
{
openpic_t *mpp;
@@ -1665,7 +1665,7 @@
struct {
const char *name;
MemoryRegionOps const *ops;
- target_phys_addr_t start_addr;
+ hwaddr start_addr;
ram_addr_t size;
} const list[] = {
{"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
diff --git a/hw/openpic.h b/hw/openpic.h
index 8556030..f50a1e4 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -13,6 +13,6 @@
qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
-qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
diff --git a/hw/openrisc_sim.c b/hw/openrisc_sim.c
index 7327740..23c66df 100644
--- a/hw/openrisc_sim.c
+++ b/hw/openrisc_sim.c
@@ -39,8 +39,8 @@
}
static void openrisc_sim_net_init(MemoryRegion *address_space,
- target_phys_addr_t base,
- target_phys_addr_t descriptors,
+ hwaddr base,
+ hwaddr descriptors,
qemu_irq irq, NICInfo *nd)
{
DeviceState *dev;
@@ -64,7 +64,7 @@
{
long kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
if (kernel_filename && !qtest_enabled()) {
kernel_size = load_elf(kernel_filename, NULL, NULL,
diff --git a/hw/palm.c b/hw/palm.c
index 032b8d6..d263051 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -27,25 +27,25 @@
#include "loader.h"
#include "exec-memory.h"
-static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readb(void *opaque, hwaddr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 3) << 3);
}
-static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readh(void *opaque, hwaddr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
-static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readw(void *opaque, hwaddr offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
}
-static void static_write(void *opaque, target_phys_addr_t offset,
+static void static_write(void *opaque, hwaddr offset,
uint32_t value)
{
#ifdef SPY
diff --git a/hw/parallel.c b/hw/parallel.c
index 219f384..c4705bc 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -511,7 +511,7 @@
}
/* Memory mapped interface */
-static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
{
ParallelState *s = opaque;
@@ -519,14 +519,14 @@
}
static void parallel_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}
-static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
{
ParallelState *s = opaque;
@@ -534,14 +534,14 @@
}
static void parallel_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}
-static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
{
ParallelState *s = opaque;
@@ -549,7 +549,7 @@
}
static void parallel_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ParallelState *s = opaque;
@@ -566,7 +566,7 @@
/* If fd is zero, it means that the parallel device uses the console */
bool parallel_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift, qemu_irq irq,
+ hwaddr base, int it_shift, qemu_irq irq,
CharDriverState *chr)
{
ParallelState *s;
diff --git a/hw/pc.c b/hw/pc.c
index 805e8ca..16de04c 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -638,13 +638,13 @@
const char *kernel_filename,
const char *initrd_filename,
const char *kernel_cmdline,
- target_phys_addr_t max_ram_size)
+ hwaddr max_ram_size)
{
uint16_t protocol;
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
uint32_t initrd_max;
uint8_t header[8192], *setup, *kernel, *initrd_data;
- target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
+ hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
FILE *f;
char *vmode;
diff --git a/hw/pc.h b/hw/pc.h
index 6cba7ce..e7993ca 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -30,7 +30,7 @@
}
bool parallel_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift, qemu_irq irq,
+ hwaddr base, int it_shift, qemu_irq irq,
CharDriverState *chr);
/* i8259.c */
@@ -68,7 +68,7 @@
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
- target_phys_addr_t mask);
+ hwaddr mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
@@ -130,10 +130,10 @@
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ hwaddr pci_hole_start,
+ hwaddr pci_hole_size,
+ hwaddr pci_hole64_start,
+ hwaddr pci_hole64_size,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
@@ -149,8 +149,8 @@
extern enum vga_retrace_method vga_retrace_method;
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+int isa_vga_mm_init(hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift,
MemoryRegion *address_space);
/* ne2000.c */
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index bf04a42..47ebc1a 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -195,7 +195,7 @@
below_4g_mem_size,
0x100000000ULL - below_4g_mem_size,
0x100000000ULL + above_4g_mem_size,
- (sizeof(target_phys_addr_t) == 4
+ (sizeof(hwaddr) == 4
? 0
: ((uint64_t)1 << 62)),
pci_memory, ram_memory);
diff --git a/hw/pc_sysfw.c b/hw/pc_sysfw.c
index b45f0ac..9d7c5f4 100644
--- a/hw/pc_sysfw.c
+++ b/hw/pc_sysfw.c
@@ -106,7 +106,7 @@
{
BlockDriverState *bdrv;
int64_t size;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
int sector_bits, sector_size;
pflash_t *system_flash;
MemoryRegion *flash_mem;
diff --git a/hw/pci.c b/hw/pci.c
index 7eeaac0..d44fd0e 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -987,7 +987,7 @@
* to >4G. Check it. TODO: we might need to support
* it in the future for e.g. PAE.
*/
- if (last_addr >= TARGET_PHYS_ADDR_MAX) {
+ if (last_addr >= HWADDR_MAX) {
return PCI_BAR_UNMAPPED;
}
diff --git a/hw/pci_host.c b/hw/pci_host.c
index 3950e94..68e328c 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -94,7 +94,7 @@
return val;
}
-static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
+static void pci_host_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
@@ -107,7 +107,7 @@
s->config_reg = val;
}
-static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
unsigned len)
{
PCIHostState *s = opaque;
@@ -118,7 +118,7 @@
return val;
}
-static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
+static void pci_host_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
@@ -129,7 +129,7 @@
}
static uint64_t pci_host_data_read(void *opaque,
- target_phys_addr_t addr, unsigned len)
+ hwaddr addr, unsigned len)
{
PCIHostState *s = opaque;
uint32_t val;
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index 28bbe72..9f7f3d3 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -53,7 +53,7 @@
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
-static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
+static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
uint64_t val, unsigned len)
{
PCIExpressHost *e = opaque;
@@ -76,7 +76,7 @@
}
static uint64_t pcie_mmcfg_data_read(void *opaque,
- target_phys_addr_t mmcfg_addr,
+ hwaddr mmcfg_addr,
unsigned len)
{
PCIExpressHost *e = opaque;
@@ -105,7 +105,7 @@
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
-#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
+#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
@@ -127,7 +127,7 @@
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
+void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr)
{
e->base_addr = addr;
memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
@@ -135,7 +135,7 @@
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr)
+ hwaddr addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index 0074508..9978b9f 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -30,10 +30,10 @@
/* express part */
/* base address where MMCONFIG area is mapped. */
- target_phys_addr_t base_addr;
+ hwaddr base_addr;
/* the size of MMCONFIG area. It's host bridge dependent */
- target_phys_addr_t size;
+ hwaddr size;
/* MMCONFIG mmio area */
MemoryRegion mmio;
@@ -41,9 +41,9 @@
int pcie_host_init(PCIExpressHost *e, uint32_t size);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
+void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr);
+ hwaddr addr);
#endif /* PCIE_HOST_H */
diff --git a/hw/pckbd.c b/hw/pckbd.c
index 69857ba..000c7f0 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -139,7 +139,7 @@
qemu_irq irq_kbd;
qemu_irq irq_mouse;
qemu_irq *a20_out;
- target_phys_addr_t mask;
+ hwaddr mask;
} KBDState;
/* update irq and KBD_STAT_[MOUSE_]OBF */
@@ -380,7 +380,7 @@
};
/* Memory mapped interface */
-static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
{
KBDState *s = opaque;
@@ -390,7 +390,7 @@
return kbd_read_data(s, 0) & 0xff;
}
-static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
{
KBDState *s = opaque;
@@ -410,7 +410,7 @@
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
- target_phys_addr_t mask)
+ hwaddr mask)
{
KBDState *s = g_malloc0(sizeof(KBDState));
diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
index 48fd447..0bf438f 100644
--- a/hw/pcnet-pci.c
+++ b/hw/pcnet-pci.c
@@ -71,7 +71,7 @@
return val;
}
-static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PCNetState *d = opaque;
@@ -98,7 +98,7 @@
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
+static void pcnet_ioport_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
PCNetState *d = opaque;
@@ -130,7 +130,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -141,7 +141,7 @@
pcnet_aprom_writeb(d, addr & 0x0f, val);
}
-static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -154,7 +154,7 @@
return val;
}
-static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -170,7 +170,7 @@
}
}
-static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -189,7 +189,7 @@
return val;
}
-static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -207,7 +207,7 @@
}
}
-static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
{
PCNetState *d = opaque;
uint32_t val;
@@ -252,13 +252,13 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
+static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
pci_dma_write(dma_opaque, addr, buf, len);
}
-static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
+static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
pci_dma_read(dma_opaque, addr, buf, len);
diff --git a/hw/pcnet.c b/hw/pcnet.c
index 40820b3..54eecd0 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -293,7 +293,7 @@
GET_FIELD((R)->msg_length, RMDM, ZEROS))
static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -323,7 +323,7 @@
}
static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -359,7 +359,7 @@
}
static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -389,7 +389,7 @@
}
static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
- target_phys_addr_t addr)
+ hwaddr addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -660,7 +660,7 @@
return 0;
}
-static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
+static inline hwaddr pcnet_rdra_addr(PCNetState *s, int idx)
{
while (idx < 1) idx += CSR_RCVRL(s);
return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
@@ -898,19 +898,19 @@
if (s->rdra) {
int bad = 0;
#if 1
- target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
- target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
- target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
+ hwaddr crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
+ hwaddr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
+ hwaddr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
#else
- target_phys_addr_t crda = s->rdra +
+ hwaddr crda = s->rdra +
(CSR_RCVRL(s) - CSR_RCVRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
- target_phys_addr_t nrda = s->rdra +
+ hwaddr nrda = s->rdra +
(CSR_RCVRL(s) - nrdc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
- target_phys_addr_t nnrd = s->rdra +
+ hwaddr nnrd = s->rdra +
(CSR_RCVRL(s) - nnrc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
#endif
@@ -970,7 +970,7 @@
{
s->csr[34] = s->csr[35] = 0;
if (s->tdra) {
- target_phys_addr_t cxda = s->tdra +
+ hwaddr cxda = s->tdra +
(CSR_XMTRL(s) - CSR_XMTRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8);
int bad = 0;
@@ -1050,7 +1050,7 @@
if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
struct pcnet_RMD rmd;
int rcvrc = CSR_RCVRC(s)-1,i;
- target_phys_addr_t nrda;
+ hwaddr nrda;
for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
if (rcvrc <= 1)
rcvrc = CSR_RCVRL(s);
@@ -1078,7 +1078,7 @@
CSR_MISSC(s)++;
} else {
uint8_t *src = s->buffer;
- target_phys_addr_t crda = CSR_CRDA(s);
+ hwaddr crda = CSR_CRDA(s);
struct pcnet_RMD rmd;
int pktcount = 0;
@@ -1118,7 +1118,7 @@
#define PCNET_RECV_STORE() do { \
int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
- target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
+ hwaddr rbadr = PHYSADDR(s, rmd.rbadr); \
s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
src += count; remaining -= count; \
SET_FIELD(&rmd.status, RMDS, OWN, 0); \
@@ -1129,7 +1129,7 @@
remaining = size;
PCNET_RECV_STORE();
if ((remaining > 0) && CSR_NRDA(s)) {
- target_phys_addr_t nrda = CSR_NRDA(s);
+ hwaddr nrda = CSR_NRDA(s);
#ifdef PCNET_DEBUG_RMD
PRINT_RMD(&rmd);
#endif
@@ -1206,7 +1206,7 @@
static void pcnet_transmit(PCNetState *s)
{
- target_phys_addr_t xmit_cxda = 0;
+ hwaddr xmit_cxda = 0;
int count = CSR_XMTRL(s)-1;
int add_crc = 0;
diff --git a/hw/pcnet.h b/hw/pcnet.h
index d0af54a..da8c3bd 100644
--- a/hw/pcnet.h
+++ b/hw/pcnet.h
@@ -42,9 +42,9 @@
MemoryRegion mmio;
uint8_t buffer[4096];
qemu_irq irq;
- void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
+ void (*phys_mem_read)(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
- void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
+ void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
void *dma_opaque;
int tx_busy;
diff --git a/hw/pcspk.c b/hw/pcspk.c
index e430324..ad6491b 100644
--- a/hw/pcspk.c
+++ b/hw/pcspk.c
@@ -121,7 +121,7 @@
return 0;
}
-static uint64_t pcspk_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pcspk_io_read(void *opaque, hwaddr addr,
unsigned size)
{
PCSpkState *s = opaque;
@@ -135,7 +135,7 @@
(ch.out << 5);
}
-static void pcspk_io_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void pcspk_io_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
PCSpkState *s = opaque;
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 5b45809..3589a4b 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -84,7 +84,7 @@
CPUMBState *env;
DriveInfo *dinfo;
int i;
- target_phys_addr_t ddr_base = MEMORY_BASEADDR;
+ hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index 71c32ce..c5fd5e7 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -66,7 +66,7 @@
CPUMBState *env;
DriveInfo *dinfo;
int i;
- target_phys_addr_t ddr_base = MEMORY_BASEADDR;
+ hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 3b437da..5e3a409 100644
--- a/hw/pflash_cfi01.c
+++ b/hw/pflash_cfi01.c
@@ -61,9 +61,9 @@
struct pflash_t {
BlockDriverState *bs;
- target_phys_addr_t base;
- target_phys_addr_t sector_len;
- target_phys_addr_t total_len;
+ hwaddr base;
+ hwaddr sector_len;
+ hwaddr total_len;
int width;
int wcycle; /* if 0, the flash is read normally */
int bypass;
@@ -73,7 +73,7 @@
uint16_t ident[4];
uint8_t cfi_len;
uint8_t cfi_table[0x52];
- target_phys_addr_t counter;
+ hwaddr counter;
unsigned int writeblock_size;
QEMUTimer *timer;
MemoryRegion mem;
@@ -96,10 +96,10 @@
pfl->cmd = 0;
}
-static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
+static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
int width, int be)
{
- target_phys_addr_t boff;
+ hwaddr boff;
uint32_t ret;
uint8_t *p;
@@ -211,7 +211,7 @@
}
}
-static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
+static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
uint32_t value, int width, int be)
{
uint8_t *p = pfl->storage;
@@ -249,7 +249,7 @@
}
-static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
+static void pflash_write(pflash_t *pfl, hwaddr offset,
uint32_t value, int width, int be)
{
uint8_t *p;
@@ -389,7 +389,7 @@
pfl->status |= 0x80;
if (!pfl->counter) {
- target_phys_addr_t mask = pfl->writeblock_size - 1;
+ hwaddr mask = pfl->writeblock_size - 1;
mask = ~mask;
DPRINTF("%s: block write finished\n", __func__);
@@ -445,57 +445,57 @@
}
-static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 1);
}
-static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 0);
}
-static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 1);
}
-static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 0);
}
-static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 1);
}
-static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 0);
}
-static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 1);
}
-static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 0);
}
-static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -503,7 +503,7 @@
pflash_write(pfl, addr, value, 2, 1);
}
-static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -511,7 +511,7 @@
pflash_write(pfl, addr, value, 2, 0);
}
-static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -519,7 +519,7 @@
pflash_write(pfl, addr, value, 4, 1);
}
-static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -543,16 +543,16 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-pflash_t *pflash_cfi01_register(target_phys_addr_t base,
+pflash_t *pflash_cfi01_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be)
{
pflash_t *pfl;
- target_phys_addr_t total_len;
+ hwaddr total_len;
int ret;
total_len = sector_len * nb_blocs;
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index 39337ec..9f94c06 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -56,7 +56,7 @@
struct pflash_t {
BlockDriverState *bs;
- target_phys_addr_t base;
+ hwaddr base;
uint32_t sector_len;
uint32_t chip_len;
int mappings;
@@ -89,7 +89,7 @@
static void pflash_setup_mappings(pflash_t *pfl)
{
unsigned i;
- target_phys_addr_t size = memory_region_size(&pfl->orig_mem);
+ hwaddr size = memory_region_size(&pfl->orig_mem);
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
@@ -122,10 +122,10 @@
pfl->cmd = 0;
}
-static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
+static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
int width, int be)
{
- target_phys_addr_t boff;
+ hwaddr boff;
uint32_t ret;
uint8_t *p;
@@ -242,10 +242,10 @@
}
}
-static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
+static void pflash_write (pflash_t *pfl, hwaddr offset,
uint32_t value, int width, int be)
{
- target_phys_addr_t boff;
+ hwaddr boff;
uint8_t *p;
uint8_t cmd;
@@ -477,57 +477,57 @@
}
-static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 1);
}
-static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
{
return pflash_read(opaque, addr, 1, 0);
}
-static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 1);
}
-static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 0);
}
-static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 1);
}
-static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 0);
}
-static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 1);
}
-static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 0);
}
-static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -535,7 +535,7 @@
pflash_write(pfl, addr, value, 2, 1);
}
-static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -543,7 +543,7 @@
pflash_write(pfl, addr, value, 2, 0);
}
-static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_be(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -551,7 +551,7 @@
pflash_write(pfl, addr, value, 4, 1);
}
-static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_le(void *opaque, hwaddr addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -575,9 +575,9 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-pflash_t *pflash_cfi02_register(target_phys_addr_t base,
+pflash_t *pflash_cfi02_register(hwaddr base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ hwaddr size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 5bca41d..9af5847 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -255,10 +255,10 @@
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ hwaddr pci_hole_start,
+ hwaddr pci_hole_size,
+ hwaddr pci_hole64_start,
+ hwaddr pci_hole64_size,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
{
@@ -342,10 +342,10 @@
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ hwaddr pci_hole_start,
+ hwaddr pci_hole_size,
+ hwaddr pci_hole64_start,
+ hwaddr pci_hole64_size,
MemoryRegion *pci_memory, MemoryRegion *ram_memory)
{
diff --git a/hw/pl011.c b/hw/pl011.c
index fb22736..1f7ce2f 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -54,7 +54,7 @@
qemu_set_irq(s->irq, flags != 0);
}
-static uint64_t pl011_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl011_read(void *opaque, hwaddr offset,
unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
@@ -127,7 +127,7 @@
s->read_trigger = 1;
}
-static void pl011_write(void *opaque, target_phys_addr_t offset,
+static void pl011_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
diff --git a/hw/pl022.c b/hw/pl022.c
index e2ae315..fbd7ded 100644
--- a/hw/pl022.c
+++ b/hw/pl022.c
@@ -130,7 +130,7 @@
pl022_update(s);
}
-static uint64_t pl022_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl022_read(void *opaque, hwaddr offset,
unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
@@ -174,7 +174,7 @@
}
}
-static void pl022_write(void *opaque, target_phys_addr_t offset,
+static void pl022_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
diff --git a/hw/pl031.c b/hw/pl031.c
index 6cbaf23..8bf0183 100644
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -95,7 +95,7 @@
}
}
-static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl031_read(void *opaque, hwaddr offset,
unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
@@ -133,7 +133,7 @@
return 0;
}
-static void pl031_write(void * opaque, target_phys_addr_t offset,
+static void pl031_write(void * opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
diff --git a/hw/pl041.c b/hw/pl041.c
index 9a6db1b..4436d97 100644
--- a/hw/pl041.c
+++ b/hw/pl041.c
@@ -97,7 +97,7 @@
#if defined(PL041_DEBUG_LEVEL)
-static const char *get_reg_name(target_phys_addr_t offset)
+static const char *get_reg_name(hwaddr offset)
{
if (offset <= PL041_dr1_7) {
return pl041_regs_name[offset >> 2];
@@ -327,7 +327,7 @@
pl041_isr1_update(s);
}
-static uint64_t pl041_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl041_read(void *opaque, hwaddr offset,
unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
@@ -361,7 +361,7 @@
return value;
}
-static void pl041_write(void *opaque, target_phys_addr_t offset,
+static void pl041_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
diff --git a/hw/pl050.c b/hw/pl050.c
index b13924a..470572e 100644
--- a/hw/pl050.c
+++ b/hw/pl050.c
@@ -58,7 +58,7 @@
qemu_set_irq(s->irq, raise);
}
-static uint64_t pl050_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl050_read(void *opaque, hwaddr offset,
unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
@@ -100,7 +100,7 @@
}
}
-static void pl050_write(void *opaque, target_phys_addr_t offset,
+static void pl050_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
diff --git a/hw/pl061.c b/hw/pl061.c
index 2aac7e8..7d182e7 100644
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -113,7 +113,7 @@
/* FIXME: Implement input interrupts. */
}
-static uint64_t pl061_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl061_read(void *opaque, hwaddr offset,
unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
@@ -169,7 +169,7 @@
}
}
-static void pl061_write(void *opaque, target_phys_addr_t offset,
+static void pl061_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
diff --git a/hw/pl080.c b/hw/pl080.c
index b3cf651..6abe528 100644
--- a/hw/pl080.c
+++ b/hw/pl080.c
@@ -218,7 +218,7 @@
}
}
-static uint64_t pl080_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl080_read(void *opaque, hwaddr offset,
unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
@@ -286,7 +286,7 @@
}
}
-static void pl080_write(void *opaque, target_phys_addr_t offset,
+static void pl080_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
diff --git a/hw/pl110.c b/hw/pl110.c
index a582640..82486b0 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -305,7 +305,7 @@
/* TODO: Implement interrupts. */
}
-static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl110_read(void *opaque, hwaddr offset,
unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
@@ -354,7 +354,7 @@
}
}
-static void pl110_write(void *opaque, target_phys_addr_t offset,
+static void pl110_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
diff --git a/hw/pl181.c b/hw/pl181.c
index 5a73473..8a2895c 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -285,7 +285,7 @@
}
}
-static uint64_t pl181_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl181_read(void *opaque, hwaddr offset,
unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
@@ -369,7 +369,7 @@
}
}
-static void pl181_write(void *opaque, target_phys_addr_t offset,
+static void pl181_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
diff --git a/hw/pl190.c b/hw/pl190.c
index 961da5b..213229b 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -85,7 +85,7 @@
pl190_update(s);
}
-static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl190_read(void *opaque, hwaddr offset,
unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
@@ -149,7 +149,7 @@
}
}
-static void pl190_write(void *opaque, target_phys_addr_t offset,
+static void pl190_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 846f53a..d655e3f 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -108,9 +108,9 @@
static int ppce500_load_device_tree(CPUPPCState *env,
PPCE500Params *params,
- target_phys_addr_t addr,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size)
+ hwaddr addr,
+ hwaddr initrd_base,
+ hwaddr initrd_size)
{
int ret = -1;
uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
@@ -346,7 +346,7 @@
}
/* Create -kernel TLB entries for BookE. */
-static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
+static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
{
return 63 - clz64(size >> 10);
}
@@ -355,7 +355,7 @@
{
struct boot_info *bi = env->load_info;
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
- target_phys_addr_t size, dt_end;
+ hwaddr size, dt_end;
int ps;
/* Our initial TLB entry needs to cover everything from 0 to
@@ -412,8 +412,8 @@
CPUPPCState *env = NULL;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- target_phys_addr_t entry=0;
- target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
+ hwaddr entry=0;
+ hwaddr loadaddr=UIMAGE_LOAD_BASE;
target_long kernel_size=0;
target_ulong dt_base = 0;
target_ulong initrd_base = 0;
diff --git a/hw/ppc405.h b/hw/ppc405.h
index 1f5dc5f..535cbfb 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -61,20 +61,20 @@
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
- target_phys_addr_t ram_bases[4],
- target_phys_addr_t ram_sizes[4],
+ hwaddr ram_bases[4],
+ hwaddr ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ hwaddr ram_bases[2],
+ hwaddr ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ hwaddr ram_bases[2],
+ hwaddr ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
ram_addr_t *offsetp);
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index e848cb0..8dc693f 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -60,7 +60,7 @@
uint8_t reg1;
};
-static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
{
ref405ep_fpga_t *fpga;
uint32_t ret;
@@ -82,7 +82,7 @@
}
static void ref405ep_fpga_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ref405ep_fpga_t *fpga;
@@ -99,7 +99,7 @@
}
}
-static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -110,13 +110,13 @@
}
static void ref405ep_fpga_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -129,7 +129,7 @@
}
static void ref405ep_fpga_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
@@ -184,7 +184,7 @@
MemoryRegion *sram = g_new(MemoryRegion, 1);
ram_addr_t bdloc;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[2], ram_sizes[2];
+ hwaddr ram_bases[2], ram_sizes[2];
target_ulong sram_size;
long bios_size;
//int phy_addr = 0;
@@ -389,7 +389,7 @@
uint8_t reg1;
};
-static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
{
taihu_cpld_t *cpld;
uint32_t ret;
@@ -411,7 +411,7 @@
}
static void taihu_cpld_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
taihu_cpld_t *cpld;
@@ -428,7 +428,7 @@
}
}
-static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -439,13 +439,13 @@
}
static void taihu_cpld_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -458,7 +458,7 @@
}
static void taihu_cpld_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
@@ -504,7 +504,7 @@
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *bios;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[2], ram_sizes[2];
+ hwaddr ram_bases[2], ram_sizes[2];
long bios_size;
target_ulong kernel_base, initrd_base;
long kernel_size, initrd_size;
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index e81409d..0f458ef 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -271,7 +271,7 @@
uint8_t pr;
};
-static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readb (void *opaque, hwaddr addr)
{
ppc4xx_opba_t *opba;
uint32_t ret;
@@ -296,7 +296,7 @@
}
static void opba_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ppc4xx_opba_t *opba;
@@ -317,7 +317,7 @@
}
}
-static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -331,7 +331,7 @@
}
static void opba_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -341,7 +341,7 @@
opba_writeb(opaque, addr + 1, value);
}
-static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -355,7 +355,7 @@
}
static void opba_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -382,7 +382,7 @@
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(target_phys_addr_t base)
+static void ppc4xx_opba_init(hwaddr base)
{
ppc4xx_opba_t *opba;
@@ -738,7 +738,7 @@
uint32_t isr1l;
};
-static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -748,7 +748,7 @@
}
static void ppc405_gpio_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -756,7 +756,7 @@
#endif
}
-static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -766,7 +766,7 @@
}
static void ppc405_gpio_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -774,7 +774,7 @@
#endif
}
-static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -784,7 +784,7 @@
}
static void ppc405_gpio_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -804,7 +804,7 @@
{
}
-static void ppc405_gpio_init(target_phys_addr_t base)
+static void ppc405_gpio_init(hwaddr base)
{
ppc405_gpio_t *gpio;
@@ -1010,7 +1010,7 @@
uint8_t directcntl;
};
-static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
{
ppc4xx_i2c_t *i2c;
uint32_t ret;
@@ -1078,7 +1078,7 @@
}
static void ppc4xx_i2c_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ppc4xx_i2c_t *i2c;
@@ -1137,7 +1137,7 @@
}
}
-static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -1151,7 +1151,7 @@
}
static void ppc4xx_i2c_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1161,7 +1161,7 @@
ppc4xx_i2c_writeb(opaque, addr + 1, value);
}
-static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
@@ -1177,7 +1177,7 @@
}
static void ppc4xx_i2c_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1213,7 +1213,7 @@
i2c->directcntl = 0x0F;
}
-static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
+static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
@@ -1245,7 +1245,7 @@
uint32_t mask[5];
};
-static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -1255,7 +1255,7 @@
}
static void ppc4xx_gpt_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1264,7 +1264,7 @@
/* XXX: generate a bus fault */
}
-static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -1274,7 +1274,7 @@
}
static void ppc4xx_gpt_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1335,7 +1335,7 @@
/* XXX: TODO */
}
-static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
{
ppc4xx_gpt_t *gpt;
uint32_t ret;
@@ -1391,7 +1391,7 @@
}
static void ppc4xx_gpt_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ppc4xx_gpt_t *gpt;
int idx;
@@ -1488,7 +1488,7 @@
}
}
-static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
+static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
@@ -2104,8 +2104,8 @@
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
- target_phys_addr_t ram_bases[4],
- target_phys_addr_t ram_sizes[4],
+ hwaddr ram_bases[4],
+ hwaddr ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
@@ -2453,8 +2453,8 @@
CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ hwaddr ram_bases[2],
+ hwaddr ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index 5616a26..a6b1d51 100644
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -49,12 +49,12 @@
256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
};
-static target_phys_addr_t entry;
+static hwaddr entry;
-static int bamboo_load_device_tree(target_phys_addr_t addr,
+static int bamboo_load_device_tree(hwaddr addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ hwaddr initrd_base,
+ hwaddr initrd_size,
const char *kernel_cmdline)
{
int ret = -1;
@@ -123,7 +123,7 @@
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
- target_phys_addr_t pa)
+ hwaddr pa)
{
ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
@@ -168,8 +168,8 @@
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram_memories
= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
- target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
+ hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
qemu_irq *pic;
qemu_irq *irqs;
PCIBus *pcibus;
@@ -177,7 +177,7 @@
CPUPPCState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- target_phys_addr_t loadaddr = 0;
+ hwaddr loadaddr = 0;
target_long initrd_size = 0;
DeviceState *dev;
int success;
diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
index 5cd78b6..d795ced 100644
--- a/hw/ppc4xx.h
+++ b/hw/ppc4xx.h
@@ -43,22 +43,22 @@
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
MemoryRegion ram_memories[],
- target_phys_addr_t ram_bases[],
- target_phys_addr_t ram_sizes[],
+ hwaddr ram_bases[],
+ hwaddr ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
- target_phys_addr_t *ram_bases,
- target_phys_addr_t *ram_sizes,
+ hwaddr *ram_bases,
+ hwaddr *ram_sizes,
int do_init);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4],
- target_phys_addr_t config_space,
- target_phys_addr_t int_ack,
- target_phys_addr_t special_cycle,
- target_phys_addr_t registers);
+ hwaddr config_space,
+ hwaddr int_ack,
+ hwaddr special_cycle,
+ hwaddr registers);
#endif /* !defined(PPC_4XX_H) */
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 41163e6..bac8d87 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -326,8 +326,8 @@
int nbanks;
MemoryRegion containers[4]; /* used for clipping */
MemoryRegion *ram_memories;
- target_phys_addr_t ram_bases[4];
- target_phys_addr_t ram_sizes[4];
+ hwaddr ram_bases[4];
+ hwaddr ram_sizes[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
@@ -348,11 +348,11 @@
};
/* XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
+ * there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr (target_phys_addr_t ram_base,
- target_phys_addr_t ram_size)
+static uint32_t sdram_bcr (hwaddr ram_base,
+ hwaddr ram_size)
{
uint32_t bcr;
@@ -389,7 +389,7 @@
return bcr;
}
-static inline target_phys_addr_t sdram_base(uint32_t bcr)
+static inline hwaddr sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
@@ -646,8 +646,8 @@
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
- target_phys_addr_t *ram_bases,
- target_phys_addr_t *ram_sizes,
+ hwaddr *ram_bases,
+ hwaddr *ram_sizes,
int do_init)
{
ppc4xx_sdram_t *sdram;
@@ -656,12 +656,12 @@
sdram->irq = irq;
sdram->nbanks = nbanks;
sdram->ram_memories = ram_memories;
- memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
+ memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(target_phys_addr_t));
- memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
+ nbanks * sizeof(hwaddr));
+ memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(target_phys_addr_t));
+ nbanks * sizeof(hwaddr));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
@@ -680,8 +680,8 @@
* sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
MemoryRegion ram_memories[],
- target_phys_addr_t ram_bases[],
- target_phys_addr_t ram_sizes[],
+ hwaddr ram_bases[],
+ hwaddr ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
ram_addr_t size_left = ram_size;
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index a14fd42..d3ad6a0 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -92,7 +92,7 @@
#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
-static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci4xx_cfgaddr_read(void *opaque, hwaddr addr,
unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
@@ -101,7 +101,7 @@
return phb->config_reg;
}
-static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
+static void pci4xx_cfgaddr_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
@@ -116,7 +116,7 @@
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
+static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
@@ -184,7 +184,7 @@
}
}
-static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
+static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h
index 7d08418..524b236 100644
--- a/hw/ppc_mac.h
+++ b/hw/ppc_mac.h
@@ -71,10 +71,10 @@
/* Mac NVRAM */
typedef struct MacIONVRAMState MacIONVRAMState;
-MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
+MacIONVRAMState *macio_nvram_init (hwaddr size,
unsigned int it_shift);
void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
- target_phys_addr_t mem_base);
+ hwaddr mem_base);
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
uint32_t macio_nvram_read (void *opaque, uint32_t addr);
void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index a265445..15f74f9 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -82,13 +82,13 @@
#endif
/* UniN device */
-static void unin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void unin_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
}
-static uint64_t unin_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
{
uint32_t value;
@@ -115,7 +115,7 @@
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static target_phys_addr_t round_page(target_phys_addr_t addr)
+static hwaddr round_page(hwaddr addr)
{
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
@@ -143,7 +143,7 @@
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
- target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;
+ hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
PCIBus *pci_bus;
MacIONVRAMState *nvr;
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index de33408..a4f899d 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -59,7 +59,7 @@
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static target_phys_addr_t round_page(target_phys_addr_t addr)
+static hwaddr round_page(hwaddr addr)
{
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index a0d1c3d..085851a 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -115,27 +115,27 @@
} XCSR;
static void PPC_XCSR_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
-static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
{
uint32_t retval = 0;
@@ -145,7 +145,7 @@
return retval;
}
-static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
{
uint32_t retval = 0;
@@ -155,7 +155,7 @@
return retval;
}
-static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
{
uint32_t retval = 0;
@@ -343,8 +343,8 @@
return retval;
}
-static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
- target_phys_addr_t addr)
+static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
+ hwaddr addr)
{
if (sysctrl->contiguous_map == 0) {
/* 64 KB contiguous space for IOs */
@@ -357,7 +357,7 @@
return addr;
}
-static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
@@ -366,7 +366,7 @@
cpu_outb(addr, value);
}
-static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
@@ -377,7 +377,7 @@
return ret;
}
-static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writew (void *opaque, hwaddr addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
@@ -387,7 +387,7 @@
cpu_outw(addr, value);
}
-static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
@@ -399,7 +399,7 @@
return ret;
}
-static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writel (void *opaque, hwaddr addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
@@ -409,7 +409,7 @@
cpu_outl(addr, value);
}
-static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
@@ -525,7 +525,7 @@
bios_size = -1;
}
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
- target_phys_addr_t bios_addr;
+ hwaddr bios_addr;
bios_size = (bios_size + 0xfff) & ~0xfff;
bios_addr = (uint32_t)(-bios_size);
bios_size = load_image_targphys(filename, bios_addr, bios_size);
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 92b1dc0..332748a 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -91,7 +91,7 @@
typedef struct PPCE500PCIState PPCE500PCIState;
-static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
unsigned size)
{
PPCE500PCIState *pci = opaque;
@@ -160,7 +160,7 @@
return value;
}
-static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
+static void pci_reg_write4(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PPCE500PCIState *pci = opaque;
diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c
index c5b8e05..55aa9dc 100644
--- a/hw/ppce500_spin.c
+++ b/hw/ppce500_spin.c
@@ -68,18 +68,18 @@
}
/* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
-static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
+static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
{
return (ffs(size >> 10) - 1) >> 1;
}
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
- target_phys_addr_t pa,
- target_phys_addr_t len)
+ hwaddr pa,
+ hwaddr len)
{
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
- target_phys_addr_t size;
+ hwaddr size;
size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
tlb->mas1 = MAS1_VALID | size;
@@ -94,8 +94,8 @@
SpinKick *kick = data;
CPUPPCState *env = kick->env;
SpinInfo *curspin = kick->spin;
- target_phys_addr_t map_size = 64 * 1024 * 1024;
- target_phys_addr_t map_start;
+ hwaddr map_size = 64 * 1024 * 1024;
+ hwaddr map_start;
cpu_synchronize_state(env);
stl_p(&curspin->pir, env->spr[SPR_PIR]);
@@ -117,7 +117,7 @@
qemu_cpu_kick(env);
}
-static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void spin_write(void *opaque, hwaddr addr, uint64_t value,
unsigned len)
{
SpinState *s = opaque;
@@ -166,7 +166,7 @@
}
}
-static uint64_t spin_read(void *opaque, target_phys_addr_t addr, unsigned len)
+static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len)
{
SpinState *s = opaque;
uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index cc44e61..0bc479c 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -44,7 +44,7 @@
PCIDevice dev;
} RavenPCIState;
-static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
+static inline uint32_t PPC_PCIIO_config(hwaddr addr)
{
int i;
@@ -56,7 +56,7 @@
return (addr & 0x7ff) | (i << 11);
}
-static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
+static void ppc_pci_io_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
PREPPCIState *s = opaque;
@@ -64,7 +64,7 @@
pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
}
-static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
unsigned int size)
{
PREPPCIState *s = opaque;
@@ -78,7 +78,7 @@
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t ppc_intack_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
unsigned int size)
{
return pic_read_irq(isa_pic);
diff --git a/hw/puv3_dma.c b/hw/puv3_dma.c
index 85b97bf..9de63b4 100644
--- a/hw/puv3_dma.c
+++ b/hw/puv3_dma.c
@@ -24,7 +24,7 @@
uint32_t reg_CFG[PUV3_DMA_CH_NR];
} PUV3DMAState;
-static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3DMAState *s = opaque;
@@ -44,7 +44,7 @@
return ret;
}
-static void puv3_dma_write(void *opaque, target_phys_addr_t offset,
+static void puv3_dma_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3DMAState *s = opaque;
diff --git a/hw/puv3_gpio.c b/hw/puv3_gpio.c
index 9436e6c..152248d2 100644
--- a/hw/puv3_gpio.c
+++ b/hw/puv3_gpio.c
@@ -24,7 +24,7 @@
uint32_t reg_GPIR;
} PUV3GPIOState;
-static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3GPIOState *s = opaque;
@@ -48,7 +48,7 @@
return ret;
}
-static void puv3_gpio_write(void *opaque, target_phys_addr_t offset,
+static void puv3_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3GPIOState *s = opaque;
diff --git a/hw/puv3_intc.c b/hw/puv3_intc.c
index 9e0b975..07f5649 100644
--- a/hw/puv3_intc.c
+++ b/hw/puv3_intc.c
@@ -46,7 +46,7 @@
puv3_intc_update(s);
}
-static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3INTCState *s = opaque;
@@ -66,7 +66,7 @@
return ret;
}
-static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
+static void puv3_intc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3INTCState *s = opaque;
diff --git a/hw/puv3_ost.c b/hw/puv3_ost.c
index dd30cad..14c6f21 100644
--- a/hw/puv3_ost.c
+++ b/hw/puv3_ost.c
@@ -28,7 +28,7 @@
uint32_t reg_OIER;
} PUV3OSTState;
-static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3OSTState *s = opaque;
@@ -51,7 +51,7 @@
return ret;
}
-static void puv3_ost_write(void *opaque, target_phys_addr_t offset,
+static void puv3_ost_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3OSTState *s = opaque;
diff --git a/hw/puv3_pm.c b/hw/puv3_pm.c
index 621c968..87a687a 100644
--- a/hw/puv3_pm.c
+++ b/hw/puv3_pm.c
@@ -26,7 +26,7 @@
uint32_t reg_DIVCFG;
} PUV3PMState;
-static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
unsigned size)
{
PUV3PMState *s = opaque;
@@ -74,7 +74,7 @@
return ret;
}
-static void puv3_pm_write(void *opaque, target_phys_addr_t offset,
+static void puv3_pm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PUV3PMState *s = opaque;
diff --git a/hw/pxa.h b/hw/pxa.h
index 6a21205..49ac820 100644
--- a/hw/pxa.h
+++ b/hw/pxa.h
@@ -65,28 +65,28 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu);
+DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
/* pxa2xx_gpio.c */
-DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
+DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUARMState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
-DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
-DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
+DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
+DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irq);
+ hwaddr base, qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
BlockDriverState *bd, qemu_irq irq,
qemu_irq rx_dma, qemu_irq tx_dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
@@ -95,7 +95,7 @@
/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
- target_phys_addr_t base);
+ hwaddr base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
@@ -107,14 +107,14 @@
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
int size);
/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
-PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
+PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
@@ -142,16 +142,16 @@
PXA2xxKeyPadState *kp;
/* Power management */
- target_phys_addr_t pm_base;
+ hwaddr pm_base;
uint32_t pm_regs[0x40];
/* Clock management */
- target_phys_addr_t cm_base;
+ hwaddr cm_base;
uint32_t cm_regs[4];
uint32_t clkcfg;
/* Memory management */
- target_phys_addr_t mm_base;
+ hwaddr mm_base;
uint32_t mm_regs[0x1a];
/* Performance monitoring */
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 4ec904f..0fb2179 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -17,7 +17,7 @@
#include "blockdev.h"
static struct {
- target_phys_addr_t io_base;
+ hwaddr io_base;
int irqn;
} pxa255_serial[] = {
{ 0x40100000, PXA2XX_PIC_FFUART },
@@ -33,7 +33,7 @@
};
typedef struct PXASSPDef {
- target_phys_addr_t io_base;
+ hwaddr io_base;
int irqn;
} PXASSPDef;
@@ -88,7 +88,7 @@
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
-static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -107,7 +107,7 @@
return 0;
}
-static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -160,7 +160,7 @@
#define OSCC 0x08 /* Oscillator Configuration register */
#define CCSR 0x0c /* Core Clock Status register */
-static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -181,7 +181,7 @@
return 0;
}
-static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_cm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -405,7 +405,7 @@
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
-static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -422,7 +422,7 @@
return 0;
}
-static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -567,7 +567,7 @@
pxa2xx_ssp_int_update(s);
}
-static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
@@ -613,7 +613,7 @@
return 0;
}
-static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
@@ -943,7 +943,7 @@
pxa2xx_rtc_int_update(s);
}
-static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
@@ -989,7 +989,7 @@
return 0;
}
-static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
@@ -1294,7 +1294,7 @@
return 1;
}
-static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
@@ -1322,7 +1322,7 @@
return 0;
}
-static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
@@ -1449,7 +1449,7 @@
.class_init = pxa2xx_i2c_slave_class_init,
};
-PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
+PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t region_size)
{
DeviceState *dev;
@@ -1572,7 +1572,7 @@
#define SADIV 0x60 /* Serial Audio Clock Divider register */
#define SADR 0x80 /* Serial Audio Data register */
-static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
@@ -1604,7 +1604,7 @@
return 0;
}
-static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
@@ -1706,7 +1706,7 @@
}
static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
{
PXA2xxI2SState *s = (PXA2xxI2SState *)
@@ -1801,7 +1801,7 @@
#define ICSR1 0x18 /* FICP Status register 1 */
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
-static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
@@ -1839,7 +1839,7 @@
return 0;
}
-static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_fir_write(void *opaque, hwaddr addr,
uint64_t value64, unsigned size)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
@@ -1963,7 +1963,7 @@
}
static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
CharDriverState *chr)
{
diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c
index 0310154..dbea1d2 100644
--- a/hw/pxa2xx_dma.c
+++ b/hw/pxa2xx_dma.c
@@ -147,7 +147,7 @@
PXA2xxDMAState *s, int ch)
{
uint32_t desc[4];
- target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
+ hwaddr daddr = s->chan[ch].descr & ~0xf;
if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
daddr += 32;
@@ -251,7 +251,7 @@
}
}
-static uint64_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
@@ -310,7 +310,7 @@
return 7;
}
-static void pxa2xx_dma_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_dma_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
@@ -473,7 +473,7 @@
return 0;
}
-DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
+DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
{
DeviceState *dev;
@@ -487,7 +487,7 @@
return dev;
}
-DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
+DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
{
DeviceState *dev;
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index 3c90c9c..7aaf409 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -139,7 +139,7 @@
}
}
-static uint64_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
@@ -191,7 +191,7 @@
return 0;
}
-static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
@@ -249,7 +249,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
+DeviceState *pxa2xx_gpio_init(hwaddr base,
CPUARMState *env, DeviceState *pic, int lines)
{
DeviceState *dev;
diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c
index 1a997c9..257984c 100644
--- a/hw/pxa2xx_keypad.c
+++ b/hw/pxa2xx_keypad.c
@@ -174,7 +174,7 @@
}
}
-static uint64_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
@@ -236,7 +236,7 @@
return 0;
}
-static void pxa2xx_keypad_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
@@ -305,7 +305,7 @@
};
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq)
{
PXA2xxKeyPadState *s;
diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c
index ee8bf57..38c3889 100644
--- a/hw/pxa2xx_lcd.c
+++ b/hw/pxa2xx_lcd.c
@@ -23,7 +23,7 @@
uint8_t up;
uint8_t palette[1024];
uint8_t pbuffer[1024];
- void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
+ void (*redraw)(PXA2xxLCDState *s, hwaddr addr,
int *miny, int *maxy);
uint32_t descriptor;
@@ -291,7 +291,7 @@
static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
{
PXAFrameDescriptor desc;
- target_phys_addr_t descptr;
+ hwaddr descptr;
int i;
for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
@@ -323,7 +323,7 @@
}
}
-static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
@@ -417,7 +417,7 @@
return 0;
}
-static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
@@ -674,7 +674,7 @@
}
static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -701,7 +701,7 @@
}
static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -729,7 +729,7 @@
}
static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -759,7 +759,7 @@
}
static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ hwaddr addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -813,7 +813,7 @@
static void pxa2xx_update_display(void *opaque)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
- target_phys_addr_t fbptr;
+ hwaddr fbptr;
int miny, maxy;
int ch;
if (!(s->control[0] & LCCR0_ENB))
@@ -987,7 +987,7 @@
#include "pxa2xx_template.h"
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irq)
+ hwaddr base, qemu_irq irq)
{
PXA2xxLCDState *s;
diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c
index b505a4c..3589968 100644
--- a/hw/pxa2xx_mmci.c
+++ b/hw/pxa2xx_mmci.c
@@ -215,7 +215,7 @@
pxa2xx_mmci_fifo_update(s);
}
-static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
uint32_t ret;
@@ -277,7 +277,7 @@
}
static void pxa2xx_mmci_write(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
@@ -386,21 +386,21 @@
}
}
-static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readb(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readh(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readw(void *opaque, hwaddr offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
@@ -408,7 +408,7 @@
}
static void pxa2xx_mmci_writeb(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
@@ -416,7 +416,7 @@
}
static void pxa2xx_mmci_writeh(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
@@ -424,7 +424,7 @@
}
static void pxa2xx_mmci_writew(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ hwaddr offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
@@ -522,7 +522,7 @@
}
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ hwaddr base,
BlockDriverState *bd, qemu_irq irq,
qemu_irq rx_dma, qemu_irq tx_dma)
{
diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
index b15872a..3a79c72 100644
--- a/hw/pxa2xx_pcmcia.c
+++ b/hw/pxa2xx_pcmcia.c
@@ -27,7 +27,7 @@
};
static uint64_t pxa2xx_pcmcia_common_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -38,7 +38,7 @@
return 0;
}
-static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_common_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -49,7 +49,7 @@
}
static uint64_t pxa2xx_pcmcia_attr_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -60,7 +60,7 @@
return 0;
}
-static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_attr_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -71,7 +71,7 @@
}
static uint64_t pxa2xx_pcmcia_io_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ hwaddr offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -82,7 +82,7 @@
return 0;
}
-static void pxa2xx_pcmcia_io_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_io_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -120,7 +120,7 @@
}
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
- target_phys_addr_t base)
+ hwaddr base)
{
PXA2xxPCMCIAState *s;
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index e1e8830..70b2b79 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -119,7 +119,7 @@
return ichp;
}
-static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
@@ -159,7 +159,7 @@
}
}
-static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
@@ -257,7 +257,7 @@
return 0;
}
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu)
+DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
index 77b033b..8242d26 100644
--- a/hw/pxa2xx_timer.c
+++ b/hw/pxa2xx_timer.c
@@ -149,7 +149,7 @@
qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}
-static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
unsigned size)
{
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
@@ -227,7 +227,7 @@
return 0;
}
-static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_timer_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
int i, tm = 0;
diff --git a/hw/qdev-addr.c b/hw/qdev-addr.c
index b711b6b..de0ba87 100644
--- a/hw/qdev-addr.c
+++ b/hw/qdev-addr.c
@@ -1,12 +1,12 @@
#include "qdev.h"
#include "qdev-addr.h"
-#include "targphys.h"
+#include "hwaddr.h"
/* --- target physical address --- */
static int parse_taddr(DeviceState *dev, Property *prop, const char *str)
{
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
*ptr = strtoull(str, NULL, 16);
return 0;
@@ -14,7 +14,7 @@
static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t len)
{
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr);
}
@@ -23,7 +23,7 @@
{
DeviceState *dev = DEVICE(obj);
Property *prop = opaque;
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
int64_t value;
value = *ptr;
@@ -35,7 +35,7 @@
{
DeviceState *dev = DEVICE(obj);
Property *prop = opaque;
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
Error *local_err = NULL;
int64_t value;
@@ -49,12 +49,12 @@
error_propagate(errp, local_err);
return;
}
- if ((uint64_t)value <= (uint64_t) ~(target_phys_addr_t)0) {
+ if ((uint64_t)value <= (uint64_t) ~(hwaddr)0) {
*ptr = value;
} else {
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
dev->id?:"", name, value, (uint64_t) 0,
- (uint64_t) ~(target_phys_addr_t)0);
+ (uint64_t) ~(hwaddr)0);
}
}
@@ -67,7 +67,7 @@
.set = set_taddr,
};
-void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value)
+void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value)
{
Error *errp = NULL;
object_property_set_int(OBJECT(dev), value, name, &errp);
diff --git a/hw/qdev-addr.h b/hw/qdev-addr.h
index a0ddf38..ea5ecb4 100644
--- a/hw/qdev-addr.h
+++ b/hw/qdev-addr.h
@@ -1,5 +1,5 @@
#define DEFINE_PROP_TADDR(_n, _s, _f, _d) \
- DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, target_phys_addr_t)
+ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, hwaddr)
extern PropertyInfo qdev_prop_taddr;
-void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value);
+void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value);
diff --git a/hw/qxl.c b/hw/qxl.c
index 1d16863..d54daf6 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -1428,7 +1428,7 @@
qxl_rom_set_dirty(d);
}
-static void ioport_write(void *opaque, target_phys_addr_t addr,
+static void ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIQXLDevice *d = opaque;
@@ -1653,7 +1653,7 @@
}
}
-static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ioport_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIQXLDevice *qxl = opaque;
diff --git a/hw/r2d.c b/hw/r2d.c
index 3cb6942..66212e9 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -127,7 +127,7 @@
update_irl(fpga);
}
-static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
+static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
{
r2d_fpga_t *s = opaque;
@@ -146,7 +146,7 @@
}
static void
-r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
{
r2d_fpga_t *s = opaque;
@@ -178,7 +178,7 @@
};
static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irl)
+ hwaddr base, qemu_irq irl)
{
r2d_fpga_t *s;
diff --git a/hw/rc4030.c b/hw/rc4030.c
index 9f39b30..e0024c8 100644
--- a/hw/rc4030.c
+++ b/hw/rc4030.c
@@ -112,7 +112,7 @@
}
/* called for accesses to rc4030 */
-static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readl(void *opaque, hwaddr addr)
{
rc4030State *s = opaque;
uint32_t val;
@@ -250,7 +250,7 @@
return val;
}
-static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readw(void *opaque, hwaddr addr)
{
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
if (addr & 0x2)
@@ -259,13 +259,13 @@
return v & 0xffff;
}
-static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readb(void *opaque, hwaddr addr)
{
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
return (v >> (8 * (addr & 0x3))) & 0xff;
}
-static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writel(void *opaque, hwaddr addr, uint32_t val)
{
rc4030State *s = opaque;
addr &= 0x3fff;
@@ -308,7 +308,7 @@
case 0x0060:
/* HACK */
if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
- target_phys_addr_t dest = s->cache_ptag & ~0x1;
+ hwaddr dest = s->cache_ptag & ~0x1;
dest += (s->cache_maint & 0x3) << 3;
cpu_physical_memory_write(dest, &val, 4);
}
@@ -390,7 +390,7 @@
}
}
-static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writew(void *opaque, hwaddr addr, uint32_t val)
{
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
@@ -401,7 +401,7 @@
rc4030_writel(opaque, addr & ~0x3, val);
}
-static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
@@ -479,7 +479,7 @@
qemu_irq_raise(s->timer_irq);
}
-static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readw(void *opaque, hwaddr addr)
{
rc4030State *s = opaque;
uint32_t val;
@@ -517,14 +517,14 @@
return val;
}
-static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readb(void *opaque, hwaddr addr)
{
uint32_t v;
v = jazzio_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readl(void *opaque, hwaddr addr)
{
uint32_t v;
v = jazzio_readw(opaque, addr);
@@ -532,7 +532,7 @@
return v;
}
-static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writew(void *opaque, hwaddr addr, uint32_t val)
{
rc4030State *s = opaque;
addr &= 0xfff;
@@ -551,7 +551,7 @@
}
}
-static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
@@ -566,7 +566,7 @@
jazzio_writew(opaque, addr & ~0x1, val);
}
-static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writel(void *opaque, hwaddr addr, uint32_t val)
{
jazzio_writew(opaque, addr, val & 0xffff);
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@@ -672,11 +672,11 @@
qemu_put_be32(f, s->itr);
}
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
+void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write)
{
rc4030State *s = opaque;
- target_phys_addr_t entry_addr;
- target_phys_addr_t phys_addr;
+ hwaddr entry_addr;
+ hwaddr phys_addr;
dma_pagetable_entry entry;
int index;
int ncpy, i;
@@ -713,7 +713,7 @@
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
{
rc4030State *s = opaque;
- target_phys_addr_t dma_addr;
+ hwaddr dma_addr;
int dev_to_mem;
s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
diff --git a/hw/realview.c b/hw/realview.c
index 8dc4be6..baa92d4 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -145,7 +145,7 @@
sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
if (is_mpcore) {
- target_phys_addr_t periphbase;
+ hwaddr periphbase;
dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 6b28fea..10ced8b 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -2455,7 +2455,7 @@
if (descriptor == 0 && (val & 0x8))
{
- target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
+ hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
/* dump tally counters to specified memory location */
RTL8139TallyCounters_dma_write(s, tc_addr);
@@ -3219,33 +3219,33 @@
/* */
-static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
{
rtl8139_io_writeb(opaque, addr & 0xFF, val);
}
-static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
{
rtl8139_io_writew(opaque, addr & 0xFF, val);
}
-static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
{
rtl8139_io_writel(opaque, addr & 0xFF, val);
}
-static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr)
{
return rtl8139_io_readb(opaque, addr & 0xFF);
}
-static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr)
{
uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
return val;
}
-static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
{
uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
return val;
diff --git a/hw/s390-virtio-bus.c b/hw/s390-virtio-bus.c
index a245684..5849a96 100644
--- a/hw/s390-virtio-bus.c
+++ b/hw/s390-virtio-bus.c
@@ -56,7 +56,7 @@
static ram_addr_t s390_virtio_device_num_vq(VirtIOS390Device *dev);
/* length of VirtIO device pages */
-const target_phys_addr_t virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
+const hwaddr virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
static void s390_virtio_bus_reset(void *opaque)
{
@@ -67,7 +67,7 @@
void s390_virtio_reset_idx(VirtIOS390Device *dev)
{
int i;
- target_phys_addr_t idx_addr;
+ hwaddr idx_addr;
uint8_t num_vq;
num_vq = s390_virtio_device_num_vq(dev);
diff --git a/hw/s390-virtio.c b/hw/s390-virtio.c
index 39ff178..85bd13e 100644
--- a/hw/s390-virtio.c
+++ b/hw/s390-virtio.c
@@ -168,8 +168,8 @@
int shift = 0;
uint8_t *storage_keys;
void *virtio_region;
- target_phys_addr_t virtio_region_len;
- target_phys_addr_t virtio_region_start;
+ hwaddr virtio_region_len;
+ hwaddr virtio_region_start;
int i;
/* s390x ram size detection needs a 16bit multiplier + an increment. So
diff --git a/hw/sbi.c b/hw/sbi.c
index 52982a9..ca78a38 100644
--- a/hw/sbi.c
+++ b/hw/sbi.c
@@ -52,7 +52,7 @@
{
}
-static uint64_t sbi_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SBIState *s = opaque;
@@ -69,7 +69,7 @@
return ret;
}
-static void sbi_mem_write(void *opaque, target_phys_addr_t addr,
+static void sbi_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned dize)
{
SBIState *s = opaque;
diff --git a/hw/serial.c b/hw/serial.c
index 5adbfaf..ae84b22 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -734,14 +734,14 @@
}
/* Memory mapped interface */
-static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t serial_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
SerialState *s = opaque;
return serial_ioport_read(s, addr >> s->it_shift);
}
-static void serial_mm_write(void *opaque, target_phys_addr_t addr,
+static void serial_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SerialState *s = opaque;
@@ -768,7 +768,7 @@
};
SerialState *serial_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift,
+ hwaddr base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian end)
{
diff --git a/hw/serial.h b/hw/serial.h
index 55a1ac5..f1e3c4a 100644
--- a/hw/serial.h
+++ b/hw/serial.h
@@ -91,7 +91,7 @@
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr);
SerialState *serial_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift,
+ hwaddr base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian end);
diff --git a/hw/sh.h b/hw/sh.h
index 40df18c..77bf8aa 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -31,7 +31,7 @@
#define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1)
#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
+void tmu012_init(struct MemoryRegion *sysmem, hwaddr base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1);
@@ -40,7 +40,7 @@
/* sh_serial.c */
#define SH_SERIAL_FEAT_SCIF (1 << 0)
void sh_serial_init(MemoryRegion *sysmem,
- target_phys_addr_t base, int feat,
+ hwaddr base, int feat,
uint32_t freq, CharDriverState *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
diff --git a/hw/sh7750.c b/hw/sh7750.c
index e712928..8bcf0df 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -197,19 +197,19 @@
Memory
**********************************************************************/
-static void error_access(const char *kind, target_phys_addr_t addr)
+static void error_access(const char *kind, hwaddr addr)
{
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
kind, regname(addr), addr);
}
-static void ignore_access(const char *kind, target_phys_addr_t addr)
+static void ignore_access(const char *kind, hwaddr addr)
{
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
kind, regname(addr), addr);
}
-static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr)
{
switch (addr) {
default:
@@ -218,7 +218,7 @@
}
}
-static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
@@ -252,7 +252,7 @@
}
}
-static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
@@ -301,7 +301,7 @@
#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
-static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writeb(void *opaque, hwaddr addr,
uint32_t mem_value)
{
@@ -314,7 +314,7 @@
abort();
}
-static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writew(void *opaque, hwaddr addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
@@ -366,7 +366,7 @@
}
}
-static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writel(void *opaque, hwaddr addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
@@ -624,14 +624,14 @@
#define MM_UTLB_DATA (7)
#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
-static uint64_t invalid_read(void *opaque, target_phys_addr_t addr)
+static uint64_t invalid_read(void *opaque, hwaddr addr)
{
abort();
return 0;
}
-static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
unsigned size)
{
SH7750State *s = opaque;
@@ -669,13 +669,13 @@
return ret;
}
-static void invalid_write(void *opaque, target_phys_addr_t addr,
+static void invalid_write(void *opaque, hwaddr addr,
uint64_t mem_value)
{
abort();
}
-static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
+static void sh7750_mmct_write(void *opaque, hwaddr addr,
uint64_t mem_value, unsigned size)
{
SH7750State *s = opaque;
diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index 7d31ced..c3f77d5 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -219,7 +219,7 @@
#endif
}
-static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t sh_intc_read(void *opaque, hwaddr offset,
unsigned size)
{
struct intc_desc *desc = opaque;
@@ -238,7 +238,7 @@
return *valuep;
}
-static void sh_intc_write(void *opaque, target_phys_addr_t offset,
+static void sh_intc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
struct intc_desc *desc = opaque;
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index 0cfac46..fdec71b 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -41,7 +41,7 @@
uint32_t iobr;
} SHPCIState;
-static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
+static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
unsigned size)
{
SHPCIState *pcic = p;
@@ -69,7 +69,7 @@
}
}
-static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
+static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
unsigned size)
{
SHPCIState *pcic = p;
diff --git a/hw/sh_serial.c b/hw/sh_serial.c
index 1d1883d..9da5d08 100644
--- a/hw/sh_serial.c
+++ b/hw/sh_serial.c
@@ -78,7 +78,7 @@
s->rx_tail = 0;
}
-static void sh_serial_write(void *opaque, target_phys_addr_t offs,
+static void sh_serial_write(void *opaque, hwaddr offs,
uint64_t val, unsigned size)
{
sh_serial_state *s = opaque;
@@ -187,11 +187,11 @@
}
fprintf(stderr, "sh_serial: unsupported write to 0x%02"
- TARGET_PRIxPHYS "\n", offs);
+ HWADDR_PRIx "\n", offs);
abort();
}
-static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs,
+static uint64_t sh_serial_read(void *opaque, hwaddr offs,
unsigned size)
{
sh_serial_state *s = opaque;
@@ -289,7 +289,7 @@
if (ret & ~((1 << 16) - 1)) {
fprintf(stderr, "sh_serial: unsupported read from 0x%02"
- TARGET_PRIxPHYS "\n", offs);
+ HWADDR_PRIx "\n", offs);
abort();
}
@@ -353,7 +353,7 @@
};
void sh_serial_init(MemoryRegion *sysmem,
- target_phys_addr_t base, int feat,
+ hwaddr base, int feat,
uint32_t freq, CharDriverState *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
diff --git a/hw/sh_timer.c b/hw/sh_timer.c
index 64bf604..c0365b1 100644
--- a/hw/sh_timer.c
+++ b/hw/sh_timer.c
@@ -59,7 +59,7 @@
s->int_level = new_level;
}
-static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t sh_timer_read(void *opaque, hwaddr offset)
{
sh_timer_state *s = (sh_timer_state *)opaque;
@@ -79,7 +79,7 @@
}
}
-static void sh_timer_write(void *opaque, target_phys_addr_t offset,
+static void sh_timer_write(void *opaque, hwaddr offset,
uint32_t value)
{
sh_timer_state *s = (sh_timer_state *)opaque;
@@ -222,7 +222,7 @@
int feat;
} tmu012_state;
-static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
+static uint64_t tmu012_read(void *opaque, hwaddr offset,
unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -253,7 +253,7 @@
return 0;
}
-static void tmu012_write(void *opaque, target_phys_addr_t offset,
+static void tmu012_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -303,7 +303,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base,
+void tmu012_init(MemoryRegion *sysmem, hwaddr base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1)
diff --git a/hw/sharpsl.h b/hw/sharpsl.h
index 0b3a774..13981a6 100644
--- a/hw/sharpsl.h
+++ b/hw/sharpsl.h
@@ -12,6 +12,6 @@
/* zaurus.c */
#define SL_PXA_PARAM_BASE 0xa0000a00
-void sl_bootparam_write(target_phys_addr_t ptr);
+void sl_bootparam_write(hwaddr ptr);
#endif
diff --git a/hw/shpc.c b/hw/shpc.c
index a5baf24..4597bbd 100644
--- a/hw/shpc.c
+++ b/hw/shpc.c
@@ -466,13 +466,13 @@
return 0;
}
-static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t shpc_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
return shpc_read(opaque, addr, size);
}
-static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
+static void shpc_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
shpc_write(opaque, addr, val, size);
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index 7fdc3be..6aafa8b 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -78,7 +78,7 @@
static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
// per-cpu interrupt controller
-static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
SLAVIO_CPUINTCTLState *s = opaque;
@@ -98,7 +98,7 @@
return ret;
}
-static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_intctl_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SLAVIO_CPUINTCTLState *s = opaque;
@@ -135,7 +135,7 @@
};
// master system interrupt controller
-static uint64_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
SLAVIO_INTCTLState *s = opaque;
@@ -161,7 +161,7 @@
return ret;
}
-static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
SLAVIO_INTCTLState *s = opaque;
diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
index 944835e..682fb45 100644
--- a/hw/slavio_misc.c
+++ b/hw/slavio_misc.c
@@ -107,7 +107,7 @@
slavio_misc_update_irq(s);
}
-static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_cfg_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -117,7 +117,7 @@
slavio_misc_update_irq(s);
}
-static uint64_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
@@ -138,7 +138,7 @@
},
};
-static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_diag_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -147,7 +147,7 @@
s->diag = val & 0xff;
}
-static uint64_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
@@ -168,7 +168,7 @@
},
};
-static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_mdm_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -177,7 +177,7 @@
s->mctrl = val & 0xff;
}
-static uint64_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
@@ -198,7 +198,7 @@
},
};
-static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_aux1_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -215,7 +215,7 @@
s->aux1 = val & 0xff;
}
-static uint64_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
@@ -236,7 +236,7 @@
},
};
-static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -252,7 +252,7 @@
slavio_misc_update_irq(s);
}
-static uint64_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
@@ -273,7 +273,7 @@
},
};
-static void apc_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void apc_mem_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APCState *s = opaque;
@@ -282,7 +282,7 @@
qemu_irq_raise(s->cpu_halt);
}
-static uint64_t apc_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t apc_mem_readb(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t ret = 0;
@@ -301,7 +301,7 @@
}
};
-static uint64_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_sysctrl_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
@@ -318,7 +318,7 @@
return ret;
}
-static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -346,7 +346,7 @@
},
};
-static uint64_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_led_mem_readw(void *opaque, hwaddr addr,
unsigned size)
{
MiscState *s = opaque;
@@ -363,7 +363,7 @@
return ret;
}
-static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
+static void slavio_led_mem_writew(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c
index 97edebb..c07ceb1 100644
--- a/hw/slavio_timer.c
+++ b/hw/slavio_timer.c
@@ -130,7 +130,7 @@
}
}
-static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
unsigned size)
{
TimerContext *tc = opaque;
@@ -190,7 +190,7 @@
return ret;
}
-static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
TimerContext *tc = opaque;
diff --git a/hw/sm501.c b/hw/sm501.c
index 050d096..4aafe49 100644
--- a/hw/sm501.c
+++ b/hw/sm501.c
@@ -456,7 +456,7 @@
DisplayState *ds;
/* status & internal resources */
- target_phys_addr_t base;
+ hwaddr base;
uint32_t local_mem_size_index;
uint8_t * local_mem;
MemoryRegion local_mem_region;
@@ -726,7 +726,7 @@
}
}
-static uint64_t sm501_system_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -779,7 +779,7 @@
return ret;
}
-static void sm501_system_config_write(void *opaque, target_phys_addr_t addr,
+static void sm501_system_config_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -837,7 +837,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
+static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
{
SM501State * s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
@@ -850,7 +850,7 @@
}
static void sm501_palette_write(void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
SM501State * s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
@@ -863,7 +863,7 @@
*(uint32_t*)&s->dc_palette[addr] = value;
}
-static uint64_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -958,7 +958,7 @@
return ret;
}
-static void sm501_disp_ctrl_write(void *opaque, target_phys_addr_t addr,
+static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -1073,7 +1073,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -1093,7 +1093,7 @@
return ret;
}
-static void sm501_2d_engine_write(void *opaque, target_phys_addr_t addr,
+static void sm501_2d_engine_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
diff --git a/hw/smc91c111.c b/hw/smc91c111.c
index d6ef302..4ceed01 100644
--- a/hw/smc91c111.c
+++ b/hw/smc91c111.c
@@ -276,7 +276,7 @@
#define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
#define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
-static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
smc91c111_state *s = (smc91c111_state *)opaque;
@@ -451,7 +451,7 @@
hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
}
-static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readb(void *opaque, hwaddr offset)
{
smc91c111_state *s = (smc91c111_state *)opaque;
@@ -595,14 +595,14 @@
return 0;
}
-static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writew(void *opaque, hwaddr offset,
uint32_t value)
{
smc91c111_writeb(opaque, offset, value & 0xff);
smc91c111_writeb(opaque, offset + 1, value >> 8);
}
-static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writel(void *opaque, hwaddr offset,
uint32_t value)
{
/* 32-bit writes to offset 0xc only actually write to the bank select
@@ -612,7 +612,7 @@
smc91c111_writew(opaque, offset + 2, value >> 16);
}
-static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readw(void *opaque, hwaddr offset)
{
uint32_t val;
val = smc91c111_readb(opaque, offset);
@@ -620,7 +620,7 @@
return val;
}
-static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readl(void *opaque, hwaddr offset)
{
uint32_t val;
val = smc91c111_readw(opaque, offset);
diff --git a/hw/soc_dma.c b/hw/soc_dma.c
index 03bc846..50d5f84 100644
--- a/hw/soc_dma.c
+++ b/hw/soc_dma.c
@@ -64,7 +64,7 @@
struct memmap_entry_s {
enum soc_dma_port_type type;
- target_phys_addr_t addr;
+ hwaddr addr;
union {
struct {
void *opaque;
@@ -105,7 +105,7 @@
}
static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma,
- target_phys_addr_t addr)
+ hwaddr addr)
{
struct memmap_entry_s *lo;
int hi;
@@ -255,7 +255,7 @@
return &s->soc;
}
-void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base,
+void soc_dma_port_add_fifo(struct soc_dma_s *soc, hwaddr virt_base,
soc_dma_io_t fn, void *opaque, int out)
{
struct memmap_entry_s *entry;
@@ -308,7 +308,7 @@
}
void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
- target_phys_addr_t virt_base, size_t size)
+ hwaddr virt_base, size_t size)
{
struct memmap_entry_s *entry;
struct dma_s *dma = (struct dma_s *) soc;
diff --git a/hw/soc_dma.h b/hw/soc_dma.h
index 904b26c..9340b8f 100644
--- a/hw/soc_dma.h
+++ b/hw/soc_dma.h
@@ -51,7 +51,7 @@
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
- target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */
+ hwaddr vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
@@ -91,19 +91,19 @@
void soc_dma_reset(struct soc_dma_s *s);
struct soc_dma_s *soc_dma_init(int n);
-void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
+void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base,
soc_dma_io_t fn, void *opaque, int out);
void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
- target_phys_addr_t virt_base, size_t size);
+ hwaddr virt_base, size_t size);
static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
- target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
+ hwaddr virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
}
static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
- target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
+ hwaddr virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
}
diff --git a/hw/spapr.c b/hw/spapr.c
index 637b3fb..73d75e8 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -228,9 +228,9 @@
static void *spapr_create_fdt_skel(const char *cpu_model,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
- target_phys_addr_t kernel_size,
+ hwaddr initrd_base,
+ hwaddr initrd_size,
+ hwaddr kernel_size,
const char *boot_device,
const char *kernel_cmdline)
{
@@ -445,7 +445,7 @@
cpu_to_be32(0x0), cpu_to_be32(0x0),
cpu_to_be32(0x0)};
char mem_name[32];
- target_phys_addr_t node0_size, mem_start;
+ hwaddr node0_size, mem_start;
uint64_t mem_reg_property[2];
int i, off;
@@ -502,9 +502,9 @@
}
static void spapr_finalize_fdt(sPAPREnvironment *spapr,
- target_phys_addr_t fdt_addr,
- target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size)
+ hwaddr fdt_addr,
+ hwaddr rtas_addr,
+ hwaddr rtas_size)
{
int ret;
void *fdt;
@@ -679,7 +679,7 @@
int i;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
- target_phys_addr_t rma_alloc_size;
+ hwaddr rma_alloc_size;
uint32_t initrd_base = 0;
long kernel_size = 0, initrd_size = 0;
long load_limit, rtas_limit, fw_size;
diff --git a/hw/spapr.h b/hw/spapr.h
index e984e3f..8ee69bd 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -13,12 +13,12 @@
QLIST_HEAD(, sPAPRPHBState) phbs;
struct icp_state *icp;
- target_phys_addr_t ram_limit;
+ hwaddr ram_limit;
void *htab;
long htab_shift;
- target_phys_addr_t rma_size;
+ hwaddr rma_size;
int vrma_adjust;
- target_phys_addr_t fdt_addr, rtas_addr;
+ hwaddr fdt_addr, rtas_addr;
long rtas_size;
void *fdt_skel;
target_ulong entry_point;
@@ -321,8 +321,8 @@
target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
uint32_t token, uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets);
-int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size);
+int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
+ hwaddr rtas_size);
#define SPAPR_TCE_PAGE_SHIFT 12
#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
diff --git a/hw/spapr_iommu.c b/hw/spapr_iommu.c
index 33f84e2..86dc8f9 100644
--- a/hw/spapr_iommu.c
+++ b/hw/spapr_iommu.c
@@ -66,8 +66,8 @@
static int spapr_tce_translate(DMAContext *dma,
dma_addr_t addr,
- target_phys_addr_t *paddr,
- target_phys_addr_t *len,
+ hwaddr *paddr,
+ hwaddr *len,
DMADirection dir)
{
sPAPRTCETable *tcet = DO_UPCAST(sPAPRTCETable, dma, dma);
@@ -82,7 +82,7 @@
if (tcet->bypass) {
*paddr = addr;
- *len = (target_phys_addr_t)-1;
+ *len = (hwaddr)-1;
return 0;
}
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index b628f89..a08ed11 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -258,7 +258,7 @@
* This is required for msi_notify()/msix_notify() which
* will write at the addresses via spapr_msi_write().
*/
-static void spapr_msi_setmsg(PCIDevice *pdev, target_phys_addr_t addr,
+static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr,
bool msix, unsigned req_num)
{
unsigned i;
@@ -439,7 +439,7 @@
qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
}
-static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t spapr_io_read(void *opaque, hwaddr addr,
unsigned size)
{
switch (size) {
@@ -453,7 +453,7 @@
assert(0);
}
-static void spapr_io_write(void *opaque, target_phys_addr_t addr,
+static void spapr_io_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
switch (size) {
@@ -483,7 +483,7 @@
* data is set to 0.
* For MSI, the vector number is encoded in least bits in data.
*/
-static void spapr_msi_write(void *opaque, target_phys_addr_t addr,
+static void spapr_msi_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
sPAPRPHBState *phb = opaque;
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index 670dc62..e307ac8 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -42,8 +42,8 @@
char *dtbusname;
MemoryRegion memspace, iospace;
- target_phys_addr_t mem_win_addr, mem_win_size, io_win_addr, io_win_size;
- target_phys_addr_t msi_win_addr;
+ hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
+ hwaddr msi_win_addr;
MemoryRegion memwindow, iowindow, msiwindow;
uint32_t dma_liobn;
diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index b808f80..67da27b 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -249,8 +249,8 @@
rtas_next++;
}
-int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size)
+int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
+ hwaddr rtas_size)
{
int ret;
int i;
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index 1dbf69e..d11a302 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -78,7 +78,7 @@
};
/* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
@@ -98,7 +98,7 @@
}
}
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
@@ -165,7 +165,7 @@
s->dmaregs[1] += len;
}
-static uint64_t dma_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dma_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
DMAState *s = opaque;
@@ -182,7 +182,7 @@
return s->dmaregs[saddr];
}
-static void dma_mem_write(void *opaque, target_phys_addr_t addr,
+static void dma_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DMAState *s = opaque;
diff --git a/hw/sparc32_dma.h b/hw/sparc32_dma.h
index 8b72c37..9497b13 100644
--- a/hw/sparc32_dma.h
+++ b/hw/sparc32_dma.h
@@ -2,9 +2,9 @@
#define SPARC32_DMA_H
/* sparc32_dma.c */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
diff --git a/hw/spitz.c b/hw/spitz.c
index 2942626..944c274 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -60,7 +60,7 @@
ECCState ecc;
} SLNANDState;
-static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
{
SLNANDState *s = (SLNANDState *) opaque;
int ryby;
@@ -102,7 +102,7 @@
return 0;
}
-static void sl_write(void *opaque, target_phys_addr_t addr,
+static void sl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SLNANDState *s = (SLNANDState *) opaque;
diff --git a/hw/stellaris.c b/hw/stellaris.c
index bfb18b0..b038f10 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -141,7 +141,7 @@
gptm_update_irq(s);
}
-static uint64_t gptm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t gptm_read(void *opaque, hwaddr offset,
unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
@@ -190,7 +190,7 @@
}
}
-static void gptm_write(void *opaque, target_phys_addr_t offset,
+static void gptm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
@@ -410,7 +410,7 @@
}
}
-static uint64_t ssys_read(void *opaque, target_phys_addr_t offset,
+static uint64_t ssys_read(void *opaque, hwaddr offset,
unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
@@ -515,7 +515,7 @@
}
}
-static void ssys_write(void *opaque, target_phys_addr_t offset,
+static void ssys_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
@@ -701,7 +701,7 @@
#define STELLARIS_I2C_MCS_IDLE 0x20
#define STELLARIS_I2C_MCS_BUSBSY 0x40
-static uint64_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
@@ -738,7 +738,7 @@
qemu_set_irq(s->irq, level);
}
-static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
@@ -989,7 +989,7 @@
}
}
-static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
@@ -1037,7 +1037,7 @@
}
}
-static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_adc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
index bc97280..a530b10 100644
--- a/hw/stellaris_enet.c
+++ b/hw/stellaris_enet.c
@@ -130,7 +130,7 @@
return (s->np < 31);
}
-static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
@@ -198,7 +198,7 @@
}
}
-static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_enet_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
diff --git a/hw/strongarm.c b/hw/strongarm.c
index 7150eeb..4385515 100644
--- a/hw/strongarm.c
+++ b/hw/strongarm.c
@@ -59,7 +59,7 @@
#endif
static struct {
- target_phys_addr_t io_base;
+ hwaddr io_base;
int irq;
} sa_serial[] = {
{ 0x80010000, SA_PIC_UART1 },
@@ -113,7 +113,7 @@
strongarm_pic_update(s);
}
-static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
unsigned size)
{
StrongARMPICState *s = opaque;
@@ -138,7 +138,7 @@
}
}
-static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
StrongARMPICState *s = opaque;
@@ -294,7 +294,7 @@
strongarm_rtc_int_update(s);
}
-static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
StrongARMRTCState *s = opaque;
@@ -316,7 +316,7 @@
}
}
-static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_rtc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
StrongARMRTCState *s = opaque;
@@ -517,7 +517,7 @@
s->prev_level = level;
}
-static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
unsigned size)
{
StrongARMGPIOInfo *s = opaque;
@@ -559,7 +559,7 @@
return 0;
}
-static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_gpio_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
StrongARMGPIOInfo *s = opaque;
@@ -609,7 +609,7 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
+static DeviceState *strongarm_gpio_init(hwaddr base,
DeviceState *pic)
{
DeviceState *dev;
@@ -729,7 +729,7 @@
s->prev_level = level;
}
-static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
unsigned size)
{
StrongARMPPCInfo *s = opaque;
@@ -759,7 +759,7 @@
return 0;
}
-static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_ppc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
StrongARMPPCInfo *s = opaque;
@@ -1095,7 +1095,7 @@
strongarm_uart_update_int_status(s);
}
-static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
unsigned size)
{
StrongARMUARTState *s = opaque;
@@ -1137,7 +1137,7 @@
}
}
-static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
StrongARMUARTState *s = opaque;
@@ -1376,7 +1376,7 @@
strongarm_ssp_int_update(s);
}
-static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
unsigned size)
{
StrongARMSSPState *s = opaque;
@@ -1409,7 +1409,7 @@
return 0;
}
-static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_ssp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
StrongARMSSPState *s = opaque;
diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c
index 8dfa5ec..8cd70ab 100644
--- a/hw/sun4c_intctl.c
+++ b/hw/sun4c_intctl.c
@@ -61,7 +61,7 @@
static void sun4c_check_interrupts(void *opaque);
-static uint64_t sun4c_intctl_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
Sun4c_INTCTLState *s = opaque;
@@ -73,7 +73,7 @@
return ret;
}
-static void sun4c_intctl_mem_write(void *opaque, target_phys_addr_t addr,
+static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
Sun4c_INTCTLState *s = opaque;
diff --git a/hw/sun4m.c b/hw/sun4m.c
index dbe93f9..02673b2 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -87,16 +87,16 @@
#define ESCC_CLOCK 4915200
struct sun4m_hwdef {
- target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
- target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base, fd_base;
- target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
- target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
- target_phys_addr_t bpp_base, dbri_base, sx_base;
+ hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
+ hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
+ hwaddr serial_base, fd_base;
+ hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
+ hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
+ hwaddr bpp_base, dbri_base, sx_base;
struct {
- target_phys_addr_t reg_base, vram_base;
+ hwaddr reg_base, vram_base;
} vsimm[MAX_VSIMMS];
- target_phys_addr_t ecc_base;
+ hwaddr ecc_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t ecc_version;
@@ -108,13 +108,13 @@
#define MAX_IOUNITS 5
struct sun4d_hwdef {
- target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
- target_phys_addr_t counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base;
- target_phys_addr_t espdma_base, esp_base;
- target_phys_addr_t ledma_base, le_base;
- target_phys_addr_t tcx_base;
- target_phys_addr_t sbi_base;
+ hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
+ hwaddr counter_base, nvram_base, ms_kb_base;
+ hwaddr serial_base;
+ hwaddr espdma_base, esp_base;
+ hwaddr ledma_base, le_base;
+ hwaddr tcx_base;
+ hwaddr sbi_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iounit_version;
@@ -123,11 +123,11 @@
};
struct sun4c_hwdef {
- target_phys_addr_t iommu_base, slavio_base;
- target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base, fd_base;
- target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
- target_phys_addr_t tcx_base, aux1_base;
+ hwaddr iommu_base, slavio_base;
+ hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
+ hwaddr serial_base, fd_base;
+ hwaddr idreg_base, dma_base, esp_base, le_base;
+ hwaddr tcx_base, aux1_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iommu_version;
@@ -373,7 +373,7 @@
return kernel_size;
}
-static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
+static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
@@ -388,7 +388,7 @@
return s;
}
-static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
+static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
void *iommu, qemu_irq *dev_irq, int is_ledma)
{
DeviceState *dev;
@@ -406,7 +406,7 @@
return s;
}
-static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
+static void lance_init(NICInfo *nd, hwaddr leaddr,
void *dma_opaque, qemu_irq irq)
{
DeviceState *dev;
@@ -426,8 +426,8 @@
qdev_connect_gpio_out(dma_opaque, 0, reset);
}
-static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
- target_phys_addr_t addrg,
+static DeviceState *slavio_intctl_init(hwaddr addr,
+ hwaddr addrg,
qemu_irq **parent_irq)
{
DeviceState *dev;
@@ -455,7 +455,7 @@
#define SYS_TIMER_OFFSET 0x10000ULL
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
-static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
+static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
qemu_irq *cpu_irqs, unsigned int num_cpus)
{
DeviceState *dev;
@@ -470,7 +470,7 @@
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
for (i = 0; i < MAX_CPUS; i++) {
- sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
+ sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
}
}
@@ -492,9 +492,9 @@
#define MISC_MDM 0x01b00000
#define MISC_SYS 0x01f00000
-static void slavio_misc_init(target_phys_addr_t base,
- target_phys_addr_t aux1_base,
- target_phys_addr_t aux2_base, qemu_irq irq,
+static void slavio_misc_init(hwaddr base,
+ hwaddr aux1_base,
+ hwaddr aux2_base, qemu_irq irq,
qemu_irq fdc_tc)
{
DeviceState *dev;
@@ -532,7 +532,7 @@
qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
}
-static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
+static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
{
DeviceState *dev;
SysBusDevice *s;
@@ -548,7 +548,7 @@
}
}
-static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
+static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
{
DeviceState *dev;
SysBusDevice *s;
@@ -561,7 +561,7 @@
sysbus_connect_irq(s, 0, cpu_halt);
}
-static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
+static void tcx_init(hwaddr addr, int vram_size, int width,
int height, int depth)
{
DeviceState *dev;
@@ -597,7 +597,7 @@
/* NCR89C100/MACIO Internal ID register */
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
-static void idreg_init(target_phys_addr_t addr)
+static void idreg_init(hwaddr addr)
{
DeviceState *dev;
SysBusDevice *s;
@@ -646,7 +646,7 @@
} AFXState;
/* SS-5 TCX AFX register */
-static void afx_init(target_phys_addr_t addr)
+static void afx_init(hwaddr addr)
{
DeviceState *dev;
SysBusDevice *s;
@@ -690,11 +690,11 @@
/* Boot PROM (OpenBIOS) */
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
- target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
+ hwaddr *base_addr = (hwaddr *)opaque;
return addr + *base_addr - PROM_VADDR;
}
-static void prom_init(target_phys_addr_t addr, const char *bios_name)
+static void prom_init(hwaddr addr, const char *bios_name)
{
DeviceState *dev;
SysBusDevice *s;
@@ -777,7 +777,7 @@
return 0;
}
-static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
+static void ram_init(hwaddr addr, ram_addr_t RAM_size,
uint64_t max_mem)
{
DeviceState *dev;
@@ -1544,7 +1544,7 @@
},
};
-static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
+static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
{
DeviceState *dev;
SysBusDevice *s;
@@ -1605,7 +1605,7 @@
}
for (i = 0; i < MAX_IOUNITS; i++)
- if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
+ if (hwdef->iounit_bases[i] != (hwaddr)-1)
iounits[i] = iommu_init(hwdef->iounit_bases[i],
hwdef->iounit_version,
sbi_irq[0]);
@@ -1744,7 +1744,7 @@
},
};
-static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
+static DeviceState *sun4c_intctl_init(hwaddr addr,
qemu_irq *parent_irq)
{
DeviceState *dev;
@@ -1825,7 +1825,7 @@
slavio_irq[1], serial_hds[0], serial_hds[1],
ESCC_CLOCK, 1);
- if (hwdef->fd_base != (target_phys_addr_t)-1) {
+ if (hwdef->fd_base != (hwaddr)-1) {
/* there is zero or one floppy drive */
memset(fd, 0, sizeof(fd));
fd[0] = drive_get(IF_FLOPPY, 0, 0);
diff --git a/hw/sun4m.h b/hw/sun4m.h
index 504c3af..a8c3133 100644
--- a/hw/sun4m.h
+++ b/hw/sun4m.h
@@ -6,17 +6,17 @@
/* Devices used by sparc32 system. */
/* iommu.c */
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
uint8_t *buf, int len, int is_write);
static inline void sparc_iommu_memory_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
}
static inline void sparc_iommu_memory_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
diff --git a/hw/sun4m_iommu.c b/hw/sun4m_iommu.c
index ebefa91..ce6819e 100644
--- a/hw/sun4m_iommu.c
+++ b/hw/sun4m_iommu.c
@@ -130,16 +130,16 @@
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t regs[IOMMU_NREGS];
- target_phys_addr_t iostart;
+ hwaddr iostart;
qemu_irq irq;
uint32_t version;
} IOMMUState;
-static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
IOMMUState *s = opaque;
- target_phys_addr_t saddr;
+ hwaddr saddr;
uint32_t ret;
saddr = addr >> 2;
@@ -157,11 +157,11 @@
return ret;
}
-static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
+static void iommu_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
IOMMUState *s = opaque;
- target_phys_addr_t saddr;
+ hwaddr saddr;
saddr = addr >> 2;
trace_sun4m_iommu_mem_writel(saddr, val);
@@ -249,11 +249,11 @@
},
};
-static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
+static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
{
uint32_t ret;
- target_phys_addr_t iopte;
- target_phys_addr_t pa = addr;
+ hwaddr iopte;
+ hwaddr pa = addr;
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
@@ -264,17 +264,17 @@
return ret;
}
-static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
+static hwaddr iommu_translate_pa(hwaddr addr,
uint32_t pte)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
trace_sun4m_iommu_translate_pa(addr, pa, pte);
return pa;
}
-static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
+static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
int is_write)
{
trace_sun4m_iommu_bad_addr(addr);
@@ -286,12 +286,12 @@
qemu_irq_raise(s->irq);
}
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
uint8_t *buf, int len, int is_write)
{
int l;
uint32_t flags;
- target_phys_addr_t page, phys_addr;
+ hwaddr page, phys_addr;
while (len > 0) {
page = addr & IOMMU_PAGE_MASK;
diff --git a/hw/sun4u.c b/hw/sun4u.c
index eeb6496..1621171 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -632,12 +632,12 @@
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
- target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
+ hwaddr *base_addr = (hwaddr *)opaque;
return addr + *base_addr - PROM_VADDR;
}
/* Boot PROM (OpenBIOS) */
-static void prom_init(target_phys_addr_t addr, const char *bios_name)
+static void prom_init(hwaddr addr, const char *bios_name)
{
DeviceState *dev;
SysBusDevice *s;
@@ -721,7 +721,7 @@
return 0;
}
-static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
+static void ram_init(hwaddr addr, ram_addr_t RAM_size)
{
DeviceState *dev;
SysBusDevice *s;
diff --git a/hw/sysbus.c b/hw/sysbus.c
index c173840..4969f06 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -48,7 +48,7 @@
}
}
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
+void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr)
{
assert(n >= 0 && n < dev->num_mmio);
@@ -56,7 +56,7 @@
/* ??? region already mapped here. */
return;
}
- if (dev->mmio[n].addr != (target_phys_addr_t)-1) {
+ if (dev->mmio[n].addr != (hwaddr)-1) {
/* Unregister previous mapping. */
memory_region_del_subregion(get_system_memory(), dev->mmio[n].memory);
}
@@ -122,7 +122,7 @@
}
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...)
+ hwaddr addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
@@ -133,7 +133,7 @@
dev = qdev_create(NULL, name);
s = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
@@ -151,7 +151,7 @@
}
DeviceState *sysbus_try_create_varargs(const char *name,
- target_phys_addr_t addr, ...)
+ hwaddr addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
@@ -165,7 +165,7 @@
}
s = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
@@ -185,7 +185,7 @@
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
SysBusDevice *s = sysbus_from_qdev(dev);
- target_phys_addr_t size;
+ hwaddr size;
int i;
monitor_printf(mon, "%*sirq %d\n", indent, "", s->num_irq);
@@ -214,13 +214,13 @@
return g_strdup(path);
}
-void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_memory(), addr, mem);
}
-void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory_overlap(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem, unsigned priority)
{
memory_region_add_subregion_overlap(get_system_memory(), addr, mem,
@@ -232,7 +232,7 @@
memory_region_del_subregion(get_system_memory(), mem);
}
-void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_io(), addr, mem);
diff --git a/hw/sysbus.h b/hw/sysbus.h
index acfbcfb..e58baaa 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -36,7 +36,7 @@
qemu_irq *irqp[QDEV_MAX_IRQ];
int num_mmio;
struct {
- target_phys_addr_t addr;
+ hwaddr addr;
MemoryRegion *memory;
} mmio[QDEV_MAX_MMIO];
int num_pio;
@@ -56,31 +56,31 @@
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
-void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
+void sysbus_add_memory(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem);
-void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory_overlap(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem, unsigned priority);
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
-void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
MemoryRegion *mem);
void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
MemoryRegion *sysbus_address_space(SysBusDevice *dev);
/* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...);
+ hwaddr addr, ...);
DeviceState *sysbus_try_create_varargs(const char *name,
- target_phys_addr_t addr, ...);
+ hwaddr addr, ...);
static inline DeviceState *sysbus_create_simple(const char *name,
- target_phys_addr_t addr,
+ hwaddr addr,
qemu_irq irq)
{
return sysbus_create_varargs(name, addr, irq, NULL);
}
static inline DeviceState *sysbus_try_create_simple(const char *name,
- target_phys_addr_t addr,
+ hwaddr addr,
qemu_irq irq)
{
return sysbus_try_create_varargs(name, addr, irq, NULL);
diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
index 420925c..31d4f26 100644
--- a/hw/tc6393xb.c
+++ b/hw/tc6393xb.c
@@ -215,7 +215,7 @@
case SCR_ ##N(1): return s->scr.N[1]; \
case SCR_ ##N(2): return s->scr.N[2]
-static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
+static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
{
switch (addr) {
case SCR_REVID:
@@ -276,7 +276,7 @@
case SCR_ ##N(1): s->scr.N[1] = value; return; \
case SCR_ ##N(2): s->scr.N[2] = value; return
-static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
+static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
{
switch (addr) {
SCR_REG_B(ISR);
@@ -327,7 +327,7 @@
(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
}
-static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
+static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
switch (addr) {
case NAND_CFG_COMMAND:
return s->nand_enable ? 2 : 0;
@@ -340,7 +340,7 @@
fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
return 0;
}
-static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
+static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
switch (addr) {
case NAND_CFG_COMMAND:
s->nand_enable = (value & 0x2);
@@ -357,7 +357,7 @@
(uint32_t) addr, value & 0xff);
}
-static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
+static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
switch (addr) {
case NAND_DATA + 0:
case NAND_DATA + 1:
@@ -376,7 +376,7 @@
fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
return 0;
}
-static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
+static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
// (uint32_t) addr, value & 0xff);
switch (addr) {
@@ -499,7 +499,7 @@
}
-static uint64_t tc6393xb_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
unsigned size)
{
TC6393xbState *s = opaque;
@@ -522,7 +522,7 @@
return 0;
}
-static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr,
+static void tc6393xb_writeb(void *opaque, hwaddr addr,
uint64_t value, unsigned size) {
TC6393xbState *s = opaque;
diff --git a/hw/tcx.c b/hw/tcx.c
index 2db2db1..7abe865 100644
--- a/hw/tcx.c
+++ b/hw/tcx.c
@@ -36,7 +36,7 @@
typedef struct TCXState {
SysBusDevice busdev;
- target_phys_addr_t addr;
+ hwaddr addr;
DisplayState *ds;
uint8_t *vram;
uint32_t *vram24, *cplane;
@@ -432,13 +432,13 @@
s->dac_state = 0;
}
-static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
unsigned size)
{
return 0;
}
-static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
TCXState *s = opaque;
@@ -484,13 +484,13 @@
},
};
-static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t dummy_readl(void *opaque, hwaddr addr,
unsigned size)
{
return 0;
}
-static void dummy_writel(void *opaque, target_phys_addr_t addr,
+static void dummy_writel(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
}
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index 5ba8da6..325200b 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -281,7 +281,7 @@
extern CPUReadMemoryFunc * const musb_read[];
extern CPUWriteMemoryFunc * const musb_write[];
-static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readb(void *opaque, hwaddr addr)
{
TUSBState *s = (TUSBState *) opaque;
@@ -298,7 +298,7 @@
return 0;
}
-static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readh(void *opaque, hwaddr addr)
{
TUSBState *s = (TUSBState *) opaque;
@@ -315,7 +315,7 @@
return 0;
}
-static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
{
TUSBState *s = (TUSBState *) opaque;
int offset = addr & 0xfff;
@@ -438,7 +438,7 @@
return 0;
}
-static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writeb(void *opaque, hwaddr addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
@@ -459,7 +459,7 @@
}
}
-static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
@@ -480,7 +480,7 @@
}
}
-static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writew(void *opaque, hwaddr addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index d1cc680..9981d94 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -111,7 +111,7 @@
return retval;
}
-static void unin_data_write(void *opaque, target_phys_addr_t addr,
+static void unin_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
UNINState *s = opaque;
@@ -123,7 +123,7 @@
val, len);
}
-static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
+static uint64_t unin_data_read(void *opaque, hwaddr addr,
unsigned len)
{
UNINState *s = opaque;
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 8bdb806..6c65a73 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -503,7 +503,7 @@
return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
}
-static const char *addr2str(target_phys_addr_t addr)
+static const char *addr2str(hwaddr addr)
{
return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names),
addr + OPREGBASE);
@@ -663,7 +663,7 @@
return async ? s->a_fetch_addr : s->p_fetch_addr;
}
-static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
+static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
{
/* need three here due to argument count limits */
trace_usb_ehci_qh_ptrs(q, addr, qh->next,
@@ -681,7 +681,7 @@
(bool)(qh->epchar & QH_EPCHAR_I));
}
-static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
+static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
{
/* need three here due to argument count limits */
trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
@@ -698,7 +698,7 @@
(bool)(qtd->token & QTD_TOKEN_XACTERR));
}
-static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
+static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
{
trace_usb_ehci_itd(addr, itd->next,
get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
@@ -707,7 +707,7 @@
get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
}
-static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
+static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
EHCIsitd *sitd)
{
trace_usb_ehci_sitd(addr, sitd->next,
@@ -1100,14 +1100,14 @@
qemu_bh_cancel(s->async_bh);
}
-static uint64_t ehci_caps_read(void *ptr, target_phys_addr_t addr,
+static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
unsigned size)
{
EHCIState *s = ptr;
return s->caps[addr];
}
-static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr,
+static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
unsigned size)
{
EHCIState *s = ptr;
@@ -1118,7 +1118,7 @@
return val;
}
-static uint64_t ehci_port_read(void *ptr, target_phys_addr_t addr,
+static uint64_t ehci_port_read(void *ptr, hwaddr addr,
unsigned size)
{
EHCIState *s = ptr;
@@ -1157,7 +1157,7 @@
}
}
-static void ehci_port_write(void *ptr, target_phys_addr_t addr,
+static void ehci_port_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
EHCIState *s = ptr;
@@ -1202,7 +1202,7 @@
trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
}
-static void ehci_opreg_write(void *ptr, target_phys_addr_t addr,
+static void ehci_opreg_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
EHCIState *s = ptr;
diff --git a/hw/usb/hcd-musb.c b/hw/usb/hcd-musb.c
index 0bb5c7b..dc114fe 100644
--- a/hw/usb/hcd-musb.c
+++ b/hw/usb/hcd-musb.c
@@ -1236,7 +1236,7 @@
}
/* Generic control */
-static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readb(void *opaque, hwaddr addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep, i;
@@ -1298,7 +1298,7 @@
};
}
-static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
@@ -1385,7 +1385,7 @@
};
}
-static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readh(void *opaque, hwaddr addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep, i;
@@ -1439,7 +1439,7 @@
};
}
-static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writeh(void *opaque, hwaddr addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
@@ -1495,7 +1495,7 @@
};
}
-static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readw(void *opaque, hwaddr addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
@@ -1513,7 +1513,7 @@
};
}
-static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writew(void *opaque, hwaddr addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 59c7055..0cc1e5d 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -1473,7 +1473,7 @@
}
static uint64_t ohci_mem_read(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
unsigned size)
{
OHCIState *ohci = opaque;
@@ -1596,7 +1596,7 @@
}
static void ohci_mem_write(void *opaque,
- target_phys_addr_t addr,
+ hwaddr addr,
uint64_t val,
unsigned size)
{
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 3a41b06..37b3dbb 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -2364,7 +2364,7 @@
xhci_mfwrap_update(xhci);
}
-static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
+static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
{
XHCIState *xhci = ptr;
uint32_t ret;
@@ -2431,7 +2431,7 @@
return ret;
}
-static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size)
+static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
{
XHCIPort *port = ptr;
uint32_t ret;
@@ -2455,7 +2455,7 @@
return ret;
}
-static void xhci_port_write(void *ptr, target_phys_addr_t reg,
+static void xhci_port_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIPort *port = ptr;
@@ -2493,7 +2493,7 @@
}
}
-static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size)
+static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
{
XHCIState *xhci = ptr;
uint32_t ret;
@@ -2535,7 +2535,7 @@
return ret;
}
-static void xhci_oper_write(void *ptr, target_phys_addr_t reg,
+static void xhci_oper_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
@@ -2596,7 +2596,7 @@
}
}
-static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg,
+static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
unsigned size)
{
XHCIState *xhci = ptr;
@@ -2644,7 +2644,7 @@
return ret;
}
-static void xhci_runtime_write(void *ptr, target_phys_addr_t reg,
+static void xhci_runtime_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
@@ -2700,7 +2700,7 @@
}
}
-static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg,
+static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
unsigned size)
{
/* doorbells always read as 0 */
@@ -2708,7 +2708,7 @@
return 0;
}
-static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg,
+static void xhci_doorbell_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
diff --git a/hw/versatile_i2c.c b/hw/versatile_i2c.c
index 88f530a..44e7e40 100644
--- a/hw/versatile_i2c.c
+++ b/hw/versatile_i2c.c
@@ -32,7 +32,7 @@
int in;
} VersatileI2CState;
-static uint64_t versatile_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
VersatileI2CState *s = (VersatileI2CState *)opaque;
@@ -45,7 +45,7 @@
}
}
-static void versatile_i2c_write(void *opaque, target_phys_addr_t offset,
+static void versatile_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
VersatileI2CState *s = (VersatileI2CState *)opaque;
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index ae53a8b..e0c3ee3 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -21,18 +21,18 @@
MemoryRegion isa;
} PCIVPBState;
-static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
+static inline uint32_t vpb_pci_config_addr(hwaddr addr)
{
return addr & 0xffffff;
}
-static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+static void pci_vpb_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t val;
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index 756ec29..f55bd0c 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -81,7 +81,7 @@
vpb_sic_update(s);
}
-static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
@@ -103,7 +103,7 @@
}
}
-static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
+static void vpb_sic_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 36503d6..3f7cb66 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -74,7 +74,7 @@
VE_DAPROM,
};
-static target_phys_addr_t motherboard_legacy_map[] = {
+static hwaddr motherboard_legacy_map[] = {
/* CS7: 0x10000000 .. 0x10020000 */
[VE_SYSREGS] = 0x10000000,
[VE_SP810] = 0x10001000,
@@ -106,7 +106,7 @@
[VE_USB] = 0x4f000000,
};
-static target_phys_addr_t motherboard_aseries_map[] = {
+static hwaddr motherboard_aseries_map[] = {
/* CS0: 0x08000000 .. 0x0c000000 */
[VE_NORFLASH0] = 0x08000000,
/* CS4: 0x0c000000 .. 0x10000000 */
@@ -150,9 +150,9 @@
qemu_irq *pic, uint32_t *proc_id);
struct VEDBoardInfo {
- const target_phys_addr_t *motherboard_map;
- target_phys_addr_t loader_start;
- const target_phys_addr_t gic_cpu_if_addr;
+ const hwaddr *motherboard_map;
+ hwaddr loader_start;
+ const hwaddr gic_cpu_if_addr;
DBoardInitFn *init;
};
@@ -364,7 +364,7 @@
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *vram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
- const target_phys_addr_t *map = daughterboard->motherboard_map;
+ const hwaddr *map = daughterboard->motherboard_map;
daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id);
diff --git a/hw/vfio_pci.c b/hw/vfio_pci.c
index e49de0d..0473ae8 100644
--- a/hw/vfio_pci.c
+++ b/hw/vfio_pci.c
@@ -678,7 +678,7 @@
/*
* IO Port/MMIO - Beware of the endians, VFIO is always little endian
*/
-static void vfio_bar_write(void *opaque, target_phys_addr_t addr,
+static void vfio_bar_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
VFIOBAR *bar = opaque;
@@ -705,11 +705,11 @@
}
if (pwrite(bar->fd, &buf, size, bar->fd_offset + addr) != size) {
- error_report("%s(,0x%"TARGET_PRIxPHYS", 0x%"PRIx64", %d) failed: %m\n",
+ error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m\n",
__func__, addr, data, size);
}
- DPRINTF("%s(BAR%d+0x%"TARGET_PRIxPHYS", 0x%"PRIx64", %d)\n",
+ DPRINTF("%s(BAR%d+0x%"HWADDR_PRIx", 0x%"PRIx64", %d)\n",
__func__, bar->nr, addr, data, size);
/*
@@ -724,7 +724,7 @@
}
static uint64_t vfio_bar_read(void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
VFIOBAR *bar = opaque;
union {
@@ -736,7 +736,7 @@
uint64_t data = 0;
if (pread(bar->fd, &buf, size, bar->fd_offset + addr) != size) {
- error_report("%s(,0x%"TARGET_PRIxPHYS", %d) failed: %m\n",
+ error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m\n",
__func__, addr, size);
return (uint64_t)-1;
}
@@ -756,7 +756,7 @@
break;
}
- DPRINTF("%s(BAR%d+0x%"TARGET_PRIxPHYS", %d) = 0x%"PRIx64"\n",
+ DPRINTF("%s(BAR%d+0x%"HWADDR_PRIx", %d) = 0x%"PRIx64"\n",
__func__, bar->nr, addr, size, data);
/* Same as write above */
@@ -882,7 +882,7 @@
* DMA - Mapping and unmapping for the "type1" IOMMU interface used on x86
*/
static int vfio_dma_unmap(VFIOContainer *container,
- target_phys_addr_t iova, ram_addr_t size)
+ hwaddr iova, ram_addr_t size)
{
struct vfio_iommu_type1_dma_unmap unmap = {
.argsz = sizeof(unmap),
@@ -899,7 +899,7 @@
return 0;
}
-static int vfio_dma_map(VFIOContainer *container, target_phys_addr_t iova,
+static int vfio_dma_map(VFIOContainer *container, hwaddr iova,
ram_addr_t size, void *vaddr, bool readonly)
{
struct vfio_iommu_type1_dma_map map = {
@@ -939,12 +939,12 @@
{
VFIOContainer *container = container_of(listener, VFIOContainer,
iommu_data.listener);
- target_phys_addr_t iova, end;
+ hwaddr iova, end;
void *vaddr;
int ret;
if (vfio_listener_skipped_section(section)) {
- DPRINTF("vfio: SKIPPING region_add %"TARGET_PRIxPHYS" - %"PRIx64"\n",
+ DPRINTF("vfio: SKIPPING region_add %"HWADDR_PRIx" - %"PRIx64"\n",
section->offset_within_address_space,
section->offset_within_address_space + section->size - 1);
return;
@@ -968,13 +968,13 @@
section->offset_within_region +
(iova - section->offset_within_address_space);
- DPRINTF("vfio: region_add %"TARGET_PRIxPHYS" - %"TARGET_PRIxPHYS" [%p]\n",
+ DPRINTF("vfio: region_add %"HWADDR_PRIx" - %"HWADDR_PRIx" [%p]\n",
iova, end - 1, vaddr);
ret = vfio_dma_map(container, iova, end - iova, vaddr, section->readonly);
if (ret) {
- error_report("vfio_dma_map(%p, 0x%"TARGET_PRIxPHYS", "
- "0x%"TARGET_PRIxPHYS", %p) = %d (%m)\n",
+ error_report("vfio_dma_map(%p, 0x%"HWADDR_PRIx", "
+ "0x%"HWADDR_PRIx", %p) = %d (%m)\n",
container, iova, end - iova, vaddr, ret);
}
}
@@ -984,11 +984,11 @@
{
VFIOContainer *container = container_of(listener, VFIOContainer,
iommu_data.listener);
- target_phys_addr_t iova, end;
+ hwaddr iova, end;
int ret;
if (vfio_listener_skipped_section(section)) {
- DPRINTF("vfio: SKIPPING region_del %"TARGET_PRIxPHYS" - %"PRIx64"\n",
+ DPRINTF("vfio: SKIPPING region_del %"HWADDR_PRIx" - %"PRIx64"\n",
section->offset_within_address_space,
section->offset_within_address_space + section->size - 1);
return;
@@ -1008,13 +1008,13 @@
return;
}
- DPRINTF("vfio: region_del %"TARGET_PRIxPHYS" - %"TARGET_PRIxPHYS"\n",
+ DPRINTF("vfio: region_del %"HWADDR_PRIx" - %"HWADDR_PRIx"\n",
iova, end - 1);
ret = vfio_dma_unmap(container, iova, end - iova);
if (ret) {
- error_report("vfio_dma_unmap(%p, 0x%"TARGET_PRIxPHYS", "
- "0x%"TARGET_PRIxPHYS") = %d (%m)\n",
+ error_report("vfio_dma_unmap(%p, 0x%"HWADDR_PRIx", "
+ "0x%"HWADDR_PRIx") = %d (%m)\n",
container, iova, end - iova, ret);
}
}
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index 306e6ba..8ef4320 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -36,7 +36,7 @@
} ISAVGAMMState;
/* Memory mapped interface */
-static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readb (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
@@ -44,14 +44,14 @@
}
static void vga_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
}
-static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readw (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
@@ -59,14 +59,14 @@
}
static void vga_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
}
-static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readl (void *opaque, hwaddr addr)
{
ISAVGAMMState *s = opaque;
@@ -74,7 +74,7 @@
}
static void vga_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
@@ -97,8 +97,8 @@
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+static void vga_mm_init(ISAVGAMMState *s, hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift,
MemoryRegion *address_space)
{
MemoryRegion *s_ioport_ctrl, *vga_io_memory;
@@ -123,8 +123,8 @@
memory_region_set_coalescing(vga_io_memory);
}
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+int isa_vga_mm_init(hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift,
MemoryRegion *address_space)
{
ISAVGAMMState *s;
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index 5c4daee..ec29cac 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -62,7 +62,7 @@
}
};
-static uint64_t pci_vga_ioport_read(void *ptr, target_phys_addr_t addr,
+static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
unsigned size)
{
PCIVGAState *d = ptr;
@@ -80,7 +80,7 @@
return ret;
}
-static void pci_vga_ioport_write(void *ptr, target_phys_addr_t addr,
+static void pci_vga_ioport_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
PCIVGAState *d = ptr;
@@ -110,7 +110,7 @@
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t pci_vga_bochs_read(void *ptr, target_phys_addr_t addr,
+static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
unsigned size)
{
PCIVGAState *d = ptr;
@@ -120,7 +120,7 @@
return vbe_ioport_read_data(&d->vga, 0);
}
-static void pci_vga_bochs_write(void *ptr, target_phys_addr_t addr,
+static void pci_vga_bochs_write(void *ptr, hwaddr addr,
uint64_t val, unsigned size)
{
PCIVGAState *d = ptr;
diff --git a/hw/vga.c b/hw/vga.c
index a07a6fb..e4220df 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -172,7 +172,7 @@
static void vga_update_memory_access(VGACommonState *s)
{
MemoryRegion *region, *old_region = s->chain4_alias;
- target_phys_addr_t base, offset, size;
+ hwaddr base, offset, size;
s->chain4_alias = NULL;
@@ -785,7 +785,7 @@
}
/* called for accesses between 0xa0000 and 0xc0000 */
-uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
+uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
{
int memory_map_mode, plane;
uint32_t ret;
@@ -842,7 +842,7 @@
}
/* called for accesses between 0xa0000 and 0xc0000 */
-void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
+void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
{
int memory_map_mode, plane, write_mode, b, func_select, mask;
uint32_t write_mask, bit_mask, set_mask;
@@ -2152,7 +2152,7 @@
dpy_update(s->ds, 0, 0, s->last_width, height);
}
-static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vga_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
VGACommonState *s = opaque;
@@ -2160,7 +2160,7 @@
return vga_mem_readb(s, addr);
}
-static void vga_mem_write(void *opaque, target_phys_addr_t addr,
+static void vga_mem_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
VGACommonState *s = opaque;
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 144e7d3..22f1706 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -190,8 +190,8 @@
extern const VMStateDescription vmstate_vga_common;
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
-uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr);
-void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val);
+uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr);
+void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val);
void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp);
diff --git a/hw/vhost.c b/hw/vhost.c
index 0b4ac3f..16322a1 100644
--- a/hw/vhost.c
+++ b/hw/vhost.c
@@ -65,8 +65,8 @@
static int vhost_sync_dirty_bitmap(struct vhost_dev *dev,
MemoryRegionSection *section,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ hwaddr start_addr,
+ hwaddr end_addr)
{
int i;
@@ -93,8 +93,8 @@
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
- target_phys_addr_t end_addr = start_addr + section->size;
+ hwaddr start_addr = section->offset_within_address_space;
+ hwaddr end_addr = start_addr + section->size;
vhost_sync_dirty_bitmap(dev, section, start_addr, end_addr);
}
@@ -296,7 +296,7 @@
int i;
for (i = 0; i < dev->nvqs; ++i) {
struct vhost_virtqueue *vq = dev->vqs + i;
- target_phys_addr_t l;
+ hwaddr l;
void *p;
if (!ranges_overlap(start_addr, size, vq->ring_phys, vq->ring_size)) {
@@ -362,7 +362,7 @@
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ hwaddr start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
bool log_dirty = memory_region_is_logging(section->mr);
int s = offsetof(struct vhost_memory, regions) +
@@ -617,7 +617,7 @@
struct vhost_virtqueue *vq,
unsigned idx)
{
- target_phys_addr_t s, l, a;
+ hwaddr s, l, a;
int r;
struct vhost_vring_file file = {
.index = idx,
@@ -948,7 +948,7 @@
}
for (i = 0; i < hdev->n_mem_sections; ++i) {
vhost_sync_dirty_bitmap(hdev, &hdev->mem_sections[i],
- 0, (target_phys_addr_t)~0x0ull);
+ 0, (hwaddr)~0x0ull);
}
r = vdev->binding->set_guest_notifiers(vdev->binding_opaque, false);
if (r < 0) {
diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index c59e1cb..6ab8fee 100644
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -58,7 +58,7 @@
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
static void mmubooke_create_initial_mapping(CPUPPCState *env,
target_ulong va,
- target_phys_addr_t pa)
+ hwaddr pa)
{
ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
@@ -134,10 +134,10 @@
}
#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
-static int xilinx_load_device_tree(target_phys_addr_t addr,
+static int xilinx_load_device_tree(hwaddr addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ hwaddr initrd_base,
+ hwaddr initrd_size,
const char *kernel_cmdline)
{
char *path;
@@ -193,7 +193,7 @@
DeviceState *dev;
PowerPCCPU *cpu;
CPUPPCState *env;
- target_phys_addr_t ram_base = 0;
+ hwaddr ram_base = 0;
DriveInfo *dinfo;
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
@@ -233,7 +233,7 @@
if (kernel_filename) {
uint64_t entry, low, high;
- target_phys_addr_t boot_offset;
+ hwaddr boot_offset;
/* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL,
diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index 400f3c2..c7f20c3 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -255,7 +255,7 @@
{
VirtIOPCIProxy *proxy = opaque;
VirtIODevice *vdev = proxy->vdev;
- target_phys_addr_t pa;
+ hwaddr pa;
switch (addr) {
case VIRTIO_PCI_GUEST_FEATURES:
@@ -266,7 +266,7 @@
virtio_set_features(vdev, val);
break;
case VIRTIO_PCI_QUEUE_PFN:
- pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
+ pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
if (pa == 0) {
virtio_pci_stop_ioeventfd(proxy);
virtio_reset(proxy->vdev);
diff --git a/hw/virtio-scsi.c b/hw/virtio-scsi.c
index c1b47a8..b54c789 100644
--- a/hw/virtio-scsi.c
+++ b/hw/virtio-scsi.c
@@ -202,7 +202,7 @@
}
static void qemu_sgl_init_external(QEMUSGList *qsgl, struct iovec *sg,
- target_phys_addr_t *addr, int num)
+ hwaddr *addr, int num)
{
memset(qsgl, 0, sizeof(*qsgl));
while (num--) {
diff --git a/hw/virtio.c b/hw/virtio.c
index 6821092..ec8b7d8 100644
--- a/hw/virtio.c
+++ b/hw/virtio.c
@@ -53,15 +53,15 @@
typedef struct VRing
{
unsigned int num;
- target_phys_addr_t desc;
- target_phys_addr_t avail;
- target_phys_addr_t used;
+ hwaddr desc;
+ hwaddr avail;
+ hwaddr used;
} VRing;
struct VirtQueue
{
VRing vring;
- target_phys_addr_t pa;
+ hwaddr pa;
uint16_t last_avail_idx;
/* Last used index value we have signalled on */
uint16_t signalled_used;
@@ -84,7 +84,7 @@
/* virt queue functions */
static void virtqueue_init(VirtQueue *vq)
{
- target_phys_addr_t pa = vq->pa;
+ hwaddr pa = vq->pa;
vq->vring.desc = pa;
vq->vring.avail = pa + vq->vring.num * sizeof(VRingDesc);
@@ -93,51 +93,51 @@
VIRTIO_PCI_VRING_ALIGN);
}
-static inline uint64_t vring_desc_addr(target_phys_addr_t desc_pa, int i)
+static inline uint64_t vring_desc_addr(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, addr);
return ldq_phys(pa);
}
-static inline uint32_t vring_desc_len(target_phys_addr_t desc_pa, int i)
+static inline uint32_t vring_desc_len(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len);
return ldl_phys(pa);
}
-static inline uint16_t vring_desc_flags(target_phys_addr_t desc_pa, int i)
+static inline uint16_t vring_desc_flags(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, flags);
return lduw_phys(pa);
}
-static inline uint16_t vring_desc_next(target_phys_addr_t desc_pa, int i)
+static inline uint16_t vring_desc_next(hwaddr desc_pa, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, next);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_flags(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, flags);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_idx(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, idx);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_ring(VirtQueue *vq, int i)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.avail + offsetof(VRingAvail, ring[i]);
return lduw_phys(pa);
}
@@ -149,49 +149,49 @@
static inline void vring_used_ring_id(VirtQueue *vq, int i, uint32_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].id);
stl_phys(pa, val);
}
static inline void vring_used_ring_len(VirtQueue *vq, int i, uint32_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].len);
stl_phys(pa, val);
}
static uint16_t vring_used_idx(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
return lduw_phys(pa);
}
static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
stw_phys(pa, val);
}
static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
stw_phys(pa, lduw_phys(pa) | mask);
}
static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
{
- target_phys_addr_t pa;
+ hwaddr pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
stw_phys(pa, lduw_phys(pa) & ~mask);
}
static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
{
- target_phys_addr_t pa;
+ hwaddr pa;
if (!vq->notification) {
return;
}
@@ -313,7 +313,7 @@
return head;
}
-static unsigned virtqueue_next_desc(target_phys_addr_t desc_pa,
+static unsigned virtqueue_next_desc(hwaddr desc_pa,
unsigned int i, unsigned int max)
{
unsigned int next;
@@ -346,7 +346,7 @@
total_bufs = in_total = out_total = 0;
while (virtqueue_num_heads(vq, idx)) {
unsigned int max, num_bufs, indirect = 0;
- target_phys_addr_t desc_pa;
+ hwaddr desc_pa;
int i;
max = vq->vring.num;
@@ -413,11 +413,11 @@
return 0;
}
-void virtqueue_map_sg(struct iovec *sg, target_phys_addr_t *addr,
+void virtqueue_map_sg(struct iovec *sg, hwaddr *addr,
size_t num_sg, int is_write)
{
unsigned int i;
- target_phys_addr_t len;
+ hwaddr len;
for (i = 0; i < num_sg; i++) {
len = sg[i].iov_len;
@@ -432,7 +432,7 @@
int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem)
{
unsigned int i, head, max;
- target_phys_addr_t desc_pa = vq->vring.desc;
+ hwaddr desc_pa = vq->vring.desc;
if (!virtqueue_num_heads(vq, vq->last_avail_idx))
return 0;
@@ -631,13 +631,13 @@
vdev->set_config(vdev, vdev->config);
}
-void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr)
+void virtio_queue_set_addr(VirtIODevice *vdev, int n, hwaddr addr)
{
vdev->vq[n].pa = addr;
virtqueue_init(&vdev->vq[n]);
}
-target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].pa;
}
@@ -940,44 +940,44 @@
vdev->binding_opaque = opaque;
}
-target_phys_addr_t virtio_queue_get_desc_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.desc;
}
-target_phys_addr_t virtio_queue_get_avail_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_avail_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.avail;
}
-target_phys_addr_t virtio_queue_get_used_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_used_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.used;
}
-target_phys_addr_t virtio_queue_get_ring_addr(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_ring_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.desc;
}
-target_phys_addr_t virtio_queue_get_desc_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_desc_size(VirtIODevice *vdev, int n)
{
return sizeof(VRingDesc) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_avail_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_avail_size(VirtIODevice *vdev, int n)
{
return offsetof(VRingAvail, ring) +
sizeof(uint64_t) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_used_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_used_size(VirtIODevice *vdev, int n)
{
return offsetof(VRingUsed, ring) +
sizeof(VRingUsedElem) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_ring_size(VirtIODevice *vdev, int n)
+hwaddr virtio_queue_get_ring_size(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.used - vdev->vq[n].vring.desc +
virtio_queue_get_used_size(vdev, n);
diff --git a/hw/virtio.h b/hw/virtio.h
index 80de375..ac482be 100644
--- a/hw/virtio.h
+++ b/hw/virtio.h
@@ -69,7 +69,7 @@
struct VirtQueue;
-static inline target_phys_addr_t vring_align(target_phys_addr_t addr,
+static inline hwaddr vring_align(hwaddr addr,
unsigned long align)
{
return (addr + align - 1) & ~(align - 1);
@@ -84,8 +84,8 @@
unsigned int index;
unsigned int out_num;
unsigned int in_num;
- target_phys_addr_t in_addr[VIRTQUEUE_MAX_SIZE];
- target_phys_addr_t out_addr[VIRTQUEUE_MAX_SIZE];
+ hwaddr in_addr[VIRTQUEUE_MAX_SIZE];
+ hwaddr out_addr[VIRTQUEUE_MAX_SIZE];
struct iovec in_sg[VIRTQUEUE_MAX_SIZE];
struct iovec out_sg[VIRTQUEUE_MAX_SIZE];
} VirtQueueElement;
@@ -144,7 +144,7 @@
void virtqueue_fill(VirtQueue *vq, const VirtQueueElement *elem,
unsigned int len, unsigned int idx);
-void virtqueue_map_sg(struct iovec *sg, target_phys_addr_t *addr,
+void virtqueue_map_sg(struct iovec *sg, hwaddr *addr,
size_t num_sg, int is_write);
int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem);
int virtqueue_avail_bytes(VirtQueue *vq, unsigned int in_bytes,
@@ -178,8 +178,8 @@
void virtio_config_writeb(VirtIODevice *vdev, uint32_t addr, uint32_t data);
void virtio_config_writew(VirtIODevice *vdev, uint32_t addr, uint32_t data);
void virtio_config_writel(VirtIODevice *vdev, uint32_t addr, uint32_t data);
-void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr);
-target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n);
+void virtio_queue_set_addr(VirtIODevice *vdev, int n, hwaddr addr);
+hwaddr virtio_queue_get_addr(VirtIODevice *vdev, int n);
int virtio_queue_get_num(VirtIODevice *vdev, int n);
void virtio_queue_notify(VirtIODevice *vdev, int n);
uint16_t virtio_queue_vector(VirtIODevice *vdev, int n);
@@ -220,14 +220,14 @@
DEFINE_PROP_BIT("event_idx", _state, _field, \
VIRTIO_RING_F_EVENT_IDX, true)
-target_phys_addr_t virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_ring_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_avail_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_used_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_ring_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_ring_addr(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_avail_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_used_size(VirtIODevice *vdev, int n);
+hwaddr virtio_queue_get_ring_size(VirtIODevice *vdev, int n);
uint16_t virtio_queue_get_last_avail_idx(VirtIODevice *vdev, int n);
void virtio_queue_set_last_avail_idx(VirtIODevice *vdev, int n, uint16_t idx);
VirtQueue *virtio_get_queue(VirtIODevice *vdev, int n);
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 6f7074e..badaf7c 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1130,7 +1130,7 @@
}
}
-static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vmsvga_io_read(void *opaque, hwaddr addr,
unsigned size)
{
struct vmsvga_state_s *s = opaque;
@@ -1143,7 +1143,7 @@
}
}
-static void vmsvga_io_write(void *opaque, target_phys_addr_t addr,
+static void vmsvga_io_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
struct vmsvga_state_s *s = opaque;
diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index 4a83474..da15c73 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -257,14 +257,14 @@
}
}
-static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
{
i6300esb_debug ("addr = %x\n", (int) addr);
return 0;
}
-static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
{
uint32_t data = 0;
I6300State *d = vp;
@@ -282,14 +282,14 @@
return data;
}
-static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
{
i6300esb_debug("addr = %x\n", (int) addr);
return 0;
}
-static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
+static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
{
I6300State *d = vp;
@@ -301,7 +301,7 @@
d->unlock_state = 2;
}
-static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
+static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
{
I6300State *d = vp;
@@ -334,7 +334,7 @@
}
}
-static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
+static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
{
I6300State *d = vp;
diff --git a/hw/xen_apic.c b/hw/xen_apic.c
index a9e101f..fc45366 100644
--- a/hw/xen_apic.c
+++ b/hw/xen_apic.c
@@ -13,13 +13,13 @@
#include "hw/msi.h"
#include "xen.h"
-static uint64_t xen_apic_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t xen_apic_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return ~(uint64_t)0;
}
-static void xen_apic_mem_write(void *opaque, target_phys_addr_t addr,
+static void xen_apic_mem_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
if (size != sizeof(uint32_t)) {
diff --git a/hw/xen_platform.c b/hw/xen_platform.c
index 956dbfe..890eb72 100644
--- a/hw/xen_platform.c
+++ b/hw/xen_platform.c
@@ -292,7 +292,7 @@
memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
}
-static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t platform_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
DPRINTF("Warning: attempted read from physical address "
@@ -301,7 +301,7 @@
return 0;
}
-static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
+static void platform_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
diff --git a/hw/xen_pt.c b/hw/xen_pt.c
index d3d7c8b..7a3846e 100644
--- a/hw/xen_pt.c
+++ b/hw/xen_pt.c
@@ -363,7 +363,7 @@
/* register regions */
-static uint64_t xen_pt_bar_read(void *o, target_phys_addr_t addr,
+static uint64_t xen_pt_bar_read(void *o, hwaddr addr,
unsigned size)
{
PCIDevice *d = o;
@@ -373,7 +373,7 @@
addr);
return 0;
}
-static void xen_pt_bar_write(void *o, target_phys_addr_t addr, uint64_t val,
+static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val,
unsigned size)
{
PCIDevice *d = o;
diff --git a/hw/xen_pt_msi.c b/hw/xen_pt_msi.c
index 2299cc7..6807672 100644
--- a/hw/xen_pt_msi.c
+++ b/hw/xen_pt_msi.c
@@ -427,7 +427,7 @@
}
}
-static void pci_msix_write(void *opaque, target_phys_addr_t addr,
+static void pci_msix_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
XenPCIPassthroughState *s = opaque;
@@ -475,7 +475,7 @@
}
}
-static uint64_t pci_msix_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_msix_read(void *opaque, hwaddr addr,
unsigned size)
{
XenPCIPassthroughState *s = opaque;
diff --git a/hw/xgmac.c b/hw/xgmac.c
index a91ef60..ec50c74 100644
--- a/hw/xgmac.c
+++ b/hw/xgmac.c
@@ -252,7 +252,7 @@
qemu_set_irq(s->sbd_irq, !!stat);
}
-static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
{
struct XgmacState *s = opaque;
uint64_t r = 0;
@@ -271,7 +271,7 @@
return r;
}
-static void enet_write(void *opaque, target_phys_addr_t addr,
+static void enet_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XgmacState *s = opaque;
diff --git a/hw/xilinx.h b/hw/xilinx.h
index 9830047..9323fd0 100644
--- a/hw/xilinx.h
+++ b/hw/xilinx.h
@@ -3,7 +3,7 @@
#include "net.h"
static inline DeviceState *
-xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr)
+xilinx_intc_create(hwaddr base, qemu_irq irq, int kind_of_intr)
{
DeviceState *dev;
@@ -17,7 +17,7 @@
/* OPB Timer/Counter. */
static inline DeviceState *
-xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int oto, int freq)
+xilinx_timer_create(hwaddr base, qemu_irq irq, int oto, int freq)
{
DeviceState *dev;
@@ -32,7 +32,7 @@
/* XPS Ethernet Lite MAC. */
static inline DeviceState *
-xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq,
+xilinx_ethlite_create(NICInfo *nd, hwaddr base, qemu_irq irq,
int txpingpong, int rxpingpong)
{
DeviceState *dev;
@@ -51,7 +51,7 @@
static inline DeviceState *
xilinx_axiethernet_create(NICInfo *nd, StreamSlave *peer,
- target_phys_addr_t base, qemu_irq irq,
+ hwaddr base, qemu_irq irq,
int txmem, int rxmem)
{
DeviceState *dev;
@@ -75,7 +75,7 @@
static inline void
xilinx_axiethernetdma_init(DeviceState *dev, StreamSlave *peer,
- target_phys_addr_t base, qemu_irq irq,
+ hwaddr base, qemu_irq irq,
qemu_irq irq2, int freqhz)
{
Error *errp = NULL;
diff --git a/hw/xilinx_axidma.c b/hw/xilinx_axidma.c
index 0e28c51..4575da1 100644
--- a/hw/xilinx_axidma.c
+++ b/hw/xilinx_axidma.c
@@ -140,7 +140,7 @@
}
/* Map an offset addr into a channel index. */
-static inline int streamid_from_addr(target_phys_addr_t addr)
+static inline int streamid_from_addr(hwaddr addr)
{
int sid;
@@ -159,7 +159,7 @@
}
#endif
-static void stream_desc_load(struct Stream *s, target_phys_addr_t addr)
+static void stream_desc_load(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;
int i;
@@ -176,7 +176,7 @@
}
}
-static void stream_desc_store(struct Stream *s, target_phys_addr_t addr)
+static void stream_desc_store(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;
int i;
@@ -364,7 +364,7 @@
stream_update_irq(s);
}
-static uint64_t axidma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t axidma_read(void *opaque, hwaddr addr,
unsigned size)
{
struct XilinxAXIDMA *d = opaque;
@@ -399,7 +399,7 @@
}
-static void axidma_write(void *opaque, target_phys_addr_t addr,
+static void axidma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XilinxAXIDMA *d = opaque;
diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index eec155d..baae02b 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -412,7 +412,7 @@
qemu_set_irq(s->irq, !!s->regs[R_IP]);
}
-static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
uint32_t r = 0;
@@ -503,7 +503,7 @@
return r;
}
-static void enet_write(void *opaque, target_phys_addr_t addr,
+static void enet_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
diff --git a/hw/xilinx_ethlite.c b/hw/xilinx_ethlite.c
index 56ca620..13bd456 100644
--- a/hw/xilinx_ethlite.c
+++ b/hw/xilinx_ethlite.c
@@ -72,7 +72,7 @@
}
static uint64_t
-eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+eth_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_ethlite *s = opaque;
uint32_t r = 0;
@@ -100,7 +100,7 @@
}
static void
-eth_write(void *opaque, target_phys_addr_t addr,
+eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
diff --git a/hw/xilinx_intc.c b/hw/xilinx_intc.c
index 386fd30..7765079 100644
--- a/hw/xilinx_intc.c
+++ b/hw/xilinx_intc.c
@@ -74,7 +74,7 @@
}
static uint64_t
-pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+pic_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_pic *p = opaque;
uint32_t r = 0;
@@ -93,7 +93,7 @@
}
static void
-pic_write(void *opaque, target_phys_addr_t addr,
+pic_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_pic *p = opaque;
diff --git a/hw/xilinx_spi.c b/hw/xilinx_spi.c
index 5cdf967..0390274 100644
--- a/hw/xilinx_spi.c
+++ b/hw/xilinx_spi.c
@@ -193,7 +193,7 @@
}
static uint64_t
-spi_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+spi_read(void *opaque, hwaddr addr, unsigned int size)
{
XilinxSPI *s = opaque;
uint32_t r = 0;
@@ -230,7 +230,7 @@
}
static void
-spi_write(void *opaque, target_phys_addr_t addr,
+spi_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
XilinxSPI *s = opaque;
diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
index f64a782..93a4957 100644
--- a/hw/xilinx_spips.c
+++ b/hw/xilinx_spips.c
@@ -183,7 +183,7 @@
xilinx_spips_update_ixr(s);
}
-static uint64_t xilinx_spips_read(void *opaque, target_phys_addr_t addr,
+static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
unsigned size)
{
XilinxSPIPS *s = opaque;
@@ -224,7 +224,7 @@
}
-static void xilinx_spips_write(void *opaque, target_phys_addr_t addr,
+static void xilinx_spips_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
int mask = ~0;
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index 2e48ca2..2b01dc2 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -72,7 +72,7 @@
return 2 - t->one_timer_only;
}
-static inline unsigned int timer_from_addr(target_phys_addr_t addr)
+static inline unsigned int timer_from_addr(hwaddr addr)
{
/* Timers get a 4x32bit control reg area each. */
return addr >> 2;
@@ -93,7 +93,7 @@
}
static uint64_t
-timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+timer_read(void *opaque, hwaddr addr, unsigned int size)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
@@ -142,7 +142,7 @@
}
static void
-timer_write(void *opaque, target_phys_addr_t addr,
+timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct timerblock *t = opaque;
diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
index d0f32db..d20fc41 100644
--- a/hw/xilinx_uartlite.c
+++ b/hw/xilinx_uartlite.c
@@ -84,7 +84,7 @@
}
static uint64_t
-uart_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+uart_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_uartlite *s = opaque;
uint32_t r = 0;
@@ -109,7 +109,7 @@
}
static void
-uart_write(void *opaque, target_phys_addr_t addr,
+uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_uartlite *s = opaque;
diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 0c407d3..5dd2e08 100644
--- a/hw/xtensa_lx60.c
+++ b/hw/xtensa_lx60.c
@@ -58,7 +58,7 @@
s->switches = 0;
}
-static uint64_t lx60_fpga_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
unsigned size)
{
Lx60FpgaState *s = opaque;
@@ -79,7 +79,7 @@
return 0;
}
-static void lx60_fpga_write(void *opaque, target_phys_addr_t addr,
+static void lx60_fpga_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
Lx60FpgaState *s = opaque;
@@ -104,7 +104,7 @@
};
static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
- target_phys_addr_t base)
+ hwaddr base)
{
Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
@@ -117,9 +117,9 @@
}
static void lx60_net_init(MemoryRegion *address_space,
- target_phys_addr_t base,
- target_phys_addr_t descriptors,
- target_phys_addr_t buffers,
+ hwaddr base,
+ hwaddr descriptors,
+ hwaddr buffers,
qemu_irq irq, NICInfo *nd)
{
DeviceState *dev;
diff --git a/hw/zaurus.c b/hw/zaurus.c
index 72838ec..d77b34e 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -68,7 +68,7 @@
s->prev_level = level;
}
-static uint64_t scoop_read(void *opaque, target_phys_addr_t addr,
+static uint64_t scoop_read(void *opaque, hwaddr addr,
unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
@@ -102,7 +102,7 @@
return 0;
}
-static void scoop_write(void *opaque, target_phys_addr_t addr,
+static void scoop_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
@@ -285,7 +285,7 @@
.phadadj = 0x01,
};
-void sl_bootparam_write(target_phys_addr_t ptr)
+void sl_bootparam_write(hwaddr ptr)
{
cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
sizeof(struct sl_param_info));
diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c
index 8acba01..dde4306 100644
--- a/hw/zynq_slcr.c
+++ b/hw/zynq_slcr.c
@@ -246,7 +246,7 @@
}
static inline uint32_t zynq_slcr_read_imp(void *opaque,
- target_phys_addr_t offset)
+ hwaddr offset)
{
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
@@ -329,7 +329,7 @@
}
}
-static uint64_t zynq_slcr_read(void *opaque, target_phys_addr_t offset,
+static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t ret = zynq_slcr_read_imp(opaque, offset);
@@ -338,7 +338,7 @@
return ret;
}
-static void zynq_slcr_write(void *opaque, target_phys_addr_t offset,
+static void zynq_slcr_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
