commit a7b69170254b15b5a40b318ed5559084ccfc466b
author Rajnesh Kanwal <rkanwal@rivosinc.com> Mon Oct 16 12:17:31 2023 +0100
committer Alistair Francis <alistair.francis@wdc.com> Tue Nov 07 11:02:17 2023 +1000
tree c82066b4c2331a87102228576592f71a8b6e5d0a
parent e57039ddab55bb0f711b3bf46d39f887663243a0

target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-2-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/csr.c

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 30cc21e..4847b47 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1525,7 +1525,7 @@
     env->mie = (env->mie & ~mask) | (new_val & mask);
 
     if (!riscv_has_ext(env, RVH)) {
-        env->mie &= ~((uint64_t)MIP_SGEIP);
+        env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
     }
 
     return RISCV_EXCP_NONE;