commit | a5fce077b134a486794b77b49f4eae1d3c9b960c | [log] [tgz] |
---|---|---|
author | Isaku Yamahata <yamahata@valinux.co.jp> | Fri Nov 19 18:56:03 2010 +0900 |
committer | Michael S. Tsirkin <mst@redhat.com> | Mon Nov 22 10:00:07 2010 +0200 |
tree | 62634df303355039bce2770af1b9d8f18b0ee4e7 | |
parent | 9bb3358627d87d8de25fb41b7276575539d799a7 [diff] |
pci bridge: implement secondary bus reset Trigger secondary bus reset when secondary bus reset bit value changes from 0 to 1. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>