commit 9f6113c7e65a98a88bb95ff5fd8679fbb28f18d6
author Edgar E. Iglesias <edgar.iglesias@gmail.com> Tue Jan 10 10:33:37 2012 +0100
committer Edgar E. Iglesias <edgar.iglesias@gmail.com> Thu Jan 12 13:54:17 2012 +0100
tree d7ccc802aa24a50cac8dbc2f5bcf8140a477d3fa
parent 5818dee572deabb1e75a0901b43caa81fb30f419

microblaze: Break the tb at memory barriers

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

target-microblaze/translate.c

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 180ac84..96ce2ec 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1249,12 +1249,22 @@
 
 static void dec_br(DisasContext *dc)
 {
-    unsigned int dslot, link, abs;
+    unsigned int dslot, link, abs, mbar;
     int mem_index = cpu_mmu_index(dc->env);
 
     dslot = dc->ir & (1 << 20);
     abs = dc->ir & (1 << 19);
     link = dc->ir & (1 << 18);
+
+    /* Memory barrier.  */
+    mbar = (dc->ir >> 16) & 31;
+    if (mbar == 2 && dc->imm == 4) {
+        LOG_DIS("mbar %d\n", dc->rd);
+        /* Break the TB.  */
+        dc->cpustate_changed = 1;
+        return;
+    }
+
     LOG_DIS("br%s%s%s%s imm=%x\n",
              abs ? "a" : "", link ? "l" : "",
              dc->type_b ? "i" : "", dslot ? "d" : "",