)]}'
{
  "commit": "9e51e0cd4bac9dd94f593d66497f635edd871d2e",
  "tree": "f62e26c5445381d5592ff82b09a792a6b91f95e8",
  "parents": [
    "a9bfd80bd48f43ce333e8668f1b26b5cfd2d1ac2"
  ],
  "author": {
    "name": "Siarhei Volkau",
    "email": "lis8215@gmail.com",
    "time": "Thu Jun 08 13:42:04 2023 +0300"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Mon Jul 10 23:33:38 2023 +0200"
  },
  "message": "target/mips/mxu: Add D32ADD instruction\n\nThe instruction adds/subtracts two 32-bit values in XRb and XRc.\nPlacing results in XRa and XRd and updates carry bits for each\npath in the MXU control register.\n\nSigned-off-by: Siarhei Volkau \u003clis8215@gmail.com\u003e\nMessage-Id: \u003c20230608104222.1520143-16-lis8215@gmail.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dc4fdf1dd98b546896a3881566edc8548a1954b4",
      "old_mode": 33188,
      "old_path": "target/mips/tcg/mxu_translate.c",
      "new_id": "b133f9f11d5bc46cd19d043b69efc713523b7ecc",
      "new_mode": 33188,
      "new_path": "target/mips/tcg/mxu_translate.c"
    }
  ]
}