)]}'
{
  "commit": "9dab7bbb017d11b64c52239fa4e2f910a6a004f2",
  "tree": "d6bf10ef4af71eae229415613edf9376d70e651c",
  "parents": [
    "096ae430a7b5a704af4cd94dca7200d6cb069991"
  ],
  "author": {
    "name": "Gregory Price",
    "email": "gregory.price@memverge.com",
    "time": "Thu Mar 07 15:53:04 2024 +0000"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Tue Mar 26 14:23:50 2024 +0100"
  },
  "message": "target/i386/tcg: Enable page walking from MMIO memory\n\nCXL emulation of interleave requires read and write hooks due to\nrequirement for subpage granularity. The Linux kernel stack now enables\nusing this memory as conventional memory in a separate NUMA node. If a\nprocess is deliberately forced to run from that node\n$ numactl --membind\u003d1 ls\nthe page table walk on i386 fails.\n\nUseful part of backtrace:\n\n    (cpu\u003dcpu@entry\u003d0x555556fd9000, fmt\u003dfmt@entry\u003d0x555555fe3378 \"cpu_io_recompile: could not find TB for pc\u003d%p\")\n    at ../../cpu-target.c:359\n    (retaddr\u003d0, addr\u003d19595792376, attrs\u003d..., xlat\u003d\u003coptimized out\u003e, cpu\u003d0x555556fd9000, out_offset\u003d\u003csynthetic pointer\u003e)\n    at ../../accel/tcg/cputlb.c:1339\n    (cpu\u003d0x555556fd9000, full\u003d0x7fffee0d96e0, ret_be\u003dret_be@entry\u003d0, addr\u003d19595792376, size\u003dsize@entry\u003d8, mmu_idx\u003d4, type\u003dMMU_DATA_LOAD, ra\u003d0) at ../../accel/tcg/cputlb.c:2030\n    (cpu\u003dcpu@entry\u003d0x555556fd9000, p\u003dp@entry\u003d0x7ffff56fddc0, mmu_idx\u003d\u003coptimized out\u003e, type\u003dtype@entry\u003dMMU_DATA_LOAD, memop\u003d\u003coptimized out\u003e, ra\u003dra@entry\u003d0) at ../../accel/tcg/cputlb.c:2356\n    (cpu\u003dcpu@entry\u003d0x555556fd9000, addr\u003daddr@entry\u003d19595792376, oi\u003doi@entry\u003d52, ra\u003dra@entry\u003d0, access_type\u003daccess_type@entry\u003dMMU_DATA_LOAD) at ../../accel/tcg/cputlb.c:2439\n    at ../../accel/tcg/ldst_common.c.inc:301\n    at ../../target/i386/tcg/sysemu/excp_helper.c:173\n    (err\u003d0x7ffff56fdf80, out\u003d0x7ffff56fdf70, mmu_idx\u003d0, access_type\u003dMMU_INST_FETCH, addr\u003d18446744072116178925, env\u003d0x555556fdb7c0)\n    at ../../target/i386/tcg/sysemu/excp_helper.c:578\n    (cs\u003d0x555556fd9000, addr\u003d18446744072116178925, size\u003d\u003coptimized out\u003e, access_type\u003dMMU_INST_FETCH, mmu_idx\u003d0, probe\u003d\u003coptimized out\u003e, retaddr\u003d0) at ../../target/i386/tcg/sysemu/excp_helper.c:604\n\nAvoid this by plumbing the address all the way down from\nx86_cpu_tlb_fill() where is available as retaddr to the actual accessors\nwhich provide it to probe_access_full() which already handles MMIO accesses.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/issues/2180\nResolves: https://gitlab.com/qemu-project/qemu/-/issues/2220\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nSuggested-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Gregory Price \u003cgregory.price@memverge.com\u003e\nSigned-off-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nMessage-ID: \u003c20240307155304.31241-2-Jonathan.Cameron@huawei.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8f7011d9663190bcfca00e3adc85184effc9992a",
      "old_mode": 33188,
      "old_path": "target/i386/tcg/sysemu/excp_helper.c",
      "new_id": "7a57b7dd10bd17c9694d30957e0332a4fe499b6e",
      "new_mode": 33188,
      "new_path": "target/i386/tcg/sysemu/excp_helper.c"
    }
  ]
}