)]}'
{
  "commit": "9d8ffbfc1d371131cd2b44dc40f3d2fa1b90faae",
  "tree": "0c66091522d657c1f8fbf585881c8392d72ad547",
  "parents": [
    "ece408818d27f745ef1b05fb3cc99a1e7a5bf580"
  ],
  "author": {
    "name": "Chao Liu",
    "email": "chao.liu.zevorn@gmail.com",
    "time": "Tue Feb 03 22:27:05 2026 +0800"
  },
  "committer": {
    "name": "Fabiano Rosas",
    "email": "farosas@suse.de",
    "time": "Tue Feb 17 09:37:40 2026 -0300"
  },
  "message": "tests/qtest/libqos: Add RISC-V IOMMU helper library\n\nIntroduce a libqos helper module for RISC-V IOMMU testing with\niommu-testdev. The helper provides routines to:\n\n- Build device contexts (DC) and 3-level page tables for SV39/SV39x4\n- Program command queue (CQ), fault queue (FQ), and DDTP registers\n  following the RISC-V IOMMU specification\n- Execute DMA translations and verify results\n\nThe current implementation supports SV39 for S-stage and SV39x4 for\nG-stage translation. Support for SV48/SV48x4/SV57/SV57x4 can be added\nin future patches.\n\nSigned-off-by: Chao Liu \u003cchao.liu.zevorn@gmail.com\u003e\nReviewed-by: Tao Tang \u003ctangtao1634@phytium.com.cn\u003e\nReviewed-by: Fabiano Rosas \u003cfarosas@suse.de\u003e\nReviewed-by: Daniel Henrique Barboza \u003cdaniel.barboza@oss.qualcomm.com\u003e\nLink: https://lore.kernel.org/qemu-devel/a2edf8c44f0bce26dccb91a7d13edb58be50c1a3.1770127918.git.chao.liu.zevorn@gmail.com\nSigned-off-by: Fabiano Rosas \u003cfarosas@suse.de\u003e\n",
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