)]}'
{
  "commit": "9b9741c38f2a92eb99c74f2bf387fc7a12d7f8e2",
  "tree": "e8ad0a98df720339eeaccbf11e20ebe988a0e6df",
  "parents": [
    "608bdebb6075b757e5505f6bbc60c45a54a1390b"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Tue Oct 03 09:25:39 2023 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Thu Oct 12 12:39:45 2023 +1000"
  },
  "message": "target/riscv/tcg: remove RVG warning\n\nVendor CPUs that set RVG are displaying user warnings about other\nextensions that RVG must enable, one warning per CPU. E.g.:\n\n$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\nqemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei\n\nThis happens because we decided a while ago that, for simplicity, vendor\nCPUs could set RVG instead of setting each G extension individually in\ntheir cpu_init(). Our warning isn\u0027t taking that into account, and we\u0027re\nbugging users with a warning that we\u0027re causing ourselves.\n\nIn a closer look we conclude that this warning is not warranted in any\nother circumstance since we\u0027re just following the ISA [1], which states\nin chapter 24:\n\n\"One goal of the RISC-V project is that it be used as a stable software\ndevelopment target. For this purpose, we define a combination of a base\nISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,\nZifencei) as a \u0027general-purpose\u0027 ISA, and we use the abbreviation G for\nthe IMAFDZicsr Zifencei combination of instruction-set extensions.\"\n\nWith this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly\nenables \u0027G\u0027 is an expected behavior and the warning is unneeded. Any\nuser caught by surprise should refer to the ISA.\n\nRemove the warning when handling RVG.\n\n[1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf\n\nReported-by: Paul A. Clarke \u003cpclarke@ventanamicro.com\u003e\nSuggested-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nSigned-off-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nReviewed-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nMessage-ID: \u003c20231003122539.775932-1-dbarboza@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2e462e7d1176a59c32570f17a503ebc206dfc5a6",
      "old_mode": 33188,
      "old_path": "target/riscv/tcg/tcg-cpu.c",
      "new_id": "a042bb6cdaf0e774d959a8e62667f739aa2407c1",
      "new_mode": 33188,
      "new_path": "target/riscv/tcg/tcg-cpu.c"
    }
  ]
}