tree d9c884c619ccfdae3c8e38764d50c28591ce894c
parent 25e168ab70627bf3368944cf5b1d97490c853007
author Alex Zuepke <alex.zuepke@tum.de> 1651152437 +0200
committer Peter Maydell <peter.maydell@linaro.org> 1651739782 +0100

target/arm: read access to performance counters from EL0

The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.

Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>