commit 97bf4851fe2542635ebe33bdd1473012a2421b42
author Blue Swirl <blauwirbel@gmail.com> Sun Oct 31 09:24:14 2010 +0000
committer Blue Swirl <blauwirbel@gmail.com> Sun Oct 31 09:24:14 2010 +0000
tree 9116cd7180ec1b2d4c8d65e52fc5b69d2a571a7f
parent b45e9c05dbacba8e992f0bffeca04c6379c3ad45

sparc32: convert debug printf statements to tracepoints

Replace debug printf statements with tracepoints.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

hw/cs4231.c

diff --git a/hw/cs4231.c b/hw/cs4231.c
index f7ce0af..2977101 100644
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -23,9 +23,7 @@
  */
 
 #include "sysbus.h"
-
-/* debug CS4231 */
-//#define DEBUG_CS
+#include "trace.h"
 
 /*
  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
@@ -46,13 +44,6 @@
 #define CS_VER 0xa0
 #define CS_CDC_VER 0x8a
 
-#ifdef DEBUG_CS
-#define DPRINTF(fmt, ...)                                       \
-    do { printf("CS: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...)
-#endif
-
 static void cs_reset(DeviceState *d)
 {
     CSState *s = container_of(d, CSState, busdev.qdev);
@@ -79,11 +70,11 @@
             ret = s->dregs[CS_RAP(s)];
             break;
         }
-        DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
+        trace_cs4231_mem_readl_dreg(CS_RAP(s), ret);
         break;
     default:
         ret = s->regs[saddr];
-        DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
+        trace_cs4231_mem_readl_reg(saddr, ret);
         break;
     }
     return ret;
@@ -95,11 +86,10 @@
     uint32_t saddr;
 
     saddr = addr >> 2;
-    DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
+    trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val);
     switch (saddr) {
     case 1:
-        DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s),
-                s->dregs[CS_RAP(s)], val);
+        trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val);
         switch(CS_RAP(s)) {
         case 11:
         case 25: // Read only