)]}'
{
  "commit": "977bbb04525682fd7a2ed8d28c0590bc2873db06",
  "tree": "12f7a767e853dffbad53da6becb9386c0403e443",
  "parents": [
    "e7443334a87b1cc43d20daacd72db44b530b7a28"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Mon Sep 25 14:56:55 2023 -0300"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair.francis@wdc.com",
    "time": "Thu Oct 12 12:00:09 2023 +1000"
  },
  "message": "target/riscv/cpu.c: add .instance_post_init()\n\nAll generic CPUs call riscv_cpu_add_user_properties(). The \u0027max\u0027 CPU\ncalls riscv_init_max_cpu_extensions(). Both can be moved to a common\ninstance_post_init() callback, implemented in riscv_cpu_post_init(),\ncalled by all CPUs. The call order then becomes:\n\nriscv_cpu_init() -\u003e cpu_init() of each CPU -\u003e .instance_post_init()\n\nIn the near future riscv_cpu_post_init() will call the init() function\nof the current accelerator, providing a hook for KVM and TCG accel\nclasses to change the init() process of the CPU.\n\nSigned-off-by: Daniel Henrique Barboza \u003cdbarboza@ventanamicro.com\u003e\nReviewed-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-ID: \u003c20230925175709.35696-6-dbarboza@ventanamicro.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "08cbd51ea1a7e9aa3f2af6ff9849bdb2626753dc",
      "old_mode": 33188,
      "old_path": "target/riscv/cpu.c",
      "new_id": "a6a26c0268f3aacafab727d48169b1a63c4086c1",
      "new_mode": 33188,
      "new_path": "target/riscv/cpu.c"
    }
  ]
}