)]}'
{
  "commit": "94452ac4cf263e8996613db8d981e4ea85bd019a",
  "tree": "01ef34d152c9c459a34a28a3e2e688551bffde6a",
  "parents": [
    "a412829406905a7edf7a33ded754f89f50a33af1"
  ],
  "author": {
    "name": "Andrew Burgess",
    "email": "aburgess@redhat.com",
    "time": "Wed Aug 31 09:41:22 2022 +0100"
  },
  "committer": {
    "name": "Alistair Francis",
    "email": "alistair@alistair23.me",
    "time": "Tue Sep 27 07:04:38 2022 +1000"
  },
  "message": "target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml\n\nWhile testing some changes to GDB\u0027s handling for the RISC-V registers\nfcsr, fflags, and frm, I spotted that QEMU includes these registers\ntwice in the target description it sends to GDB, once in the fpu\nfeature, and once in the csr feature.\n\nRight now things basically work OK, QEMU maps these registers onto two\ndifferent register numbers, e.g. fcsr maps to both 68 and 73, and GDB\ncan use either of these to access the register.\n\nHowever, GDB\u0027s target descriptions don\u0027t really work this way, each\nregister should appear just once in a target description, mapping the\nregister name onto the number GDB should use when accessing the\nregister on the target.  Duplicate register names actually result in\nduplicate registers on the GDB side, however, as the registers have\nthe same name, the user can only access one of these registers.\n\nCurrently GDB has a hack in place, specifically for RISC-V, to spot\nthe duplicate copies of these three registers, and hide them from the\nuser, ensuring the user only ever sees a single copy of each.\n\nIn this commit I propose fixing this issue on the QEMU side, and in\nthe process, simplify the fpu register handling a little.\n\nI think we should, remove fflags, frm, and fcsr from the two (32-bit\nand 64-bit) fpu feature xml files.  These files will only contain the\n32 core floating point register f0 to f31.  The fflags, frm, and fcsr\nregisters will continue to be advertised in the csr feature as they\ncurrently are.\n\nWith that change made, I will simplify riscv_gdb_get_fpu and\nriscv_gdb_set_fpu, removing the extra handling for the 3 status\nregisters.\n\nSigned-off-by: Andrew Burgess \u003caburgess@redhat.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\nMessage-Id: \u003c0fbf2a5b12e3210ff3867d5cf7022b3f3462c9c8.1661934573.git.aburgess@redhat.com\u003e\nSigned-off-by: Alistair Francis \u003calistair.francis@wdc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1eaae9119e38f78196d89ebb77e39018a7ffd211",
      "old_mode": 33188,
      "old_path": "gdb-xml/riscv-32bit-fpu.xml",
      "new_id": "84a44ba8df0d463084ab47e457bb809aeca29c8b",
      "new_mode": 33188,
      "new_path": "gdb-xml/riscv-32bit-fpu.xml"
    },
    {
      "type": "modify",
      "old_id": "794854cc011bee00ce44a41456c03274af4b4b28",
      "old_mode": 33188,
      "old_path": "gdb-xml/riscv-64bit-fpu.xml",
      "new_id": "9856a9d1d3182a0d4ac7576bed60cb070df6edf6",
      "new_mode": 33188,
      "new_path": "gdb-xml/riscv-64bit-fpu.xml"
    },
    {
      "type": "modify",
      "old_id": "9ed049c29ea5c8b9b70ac1d53b7e17162fc33a92",
      "old_mode": 33188,
      "old_path": "target/riscv/gdbstub.c",
      "new_id": "9974b7aac64f8f5a897d1e0dda489b3d6c73a8d1",
      "new_mode": 33188,
      "new_path": "target/riscv/gdbstub.c"
    }
  ]
}