commit 938dd05ea1f3a9e3c713b1d73dc2992d62efb830
author demin.han <demin.han@starfivetech.com> Mon Feb 26 01:41:14 2024 +0800
committer Alistair Francis <alistair.francis@wdc.com> Fri Mar 08 20:48:03 2024 +1000
tree 51534578d6023330daf4fc353dc8e78849815f4e
parent a506c4289dd05b3134a1b6eb0b506eaee81e224d

target/riscv: Fix shift count overflow

The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
and results in wrong vill.

Signed-off-by: demin.han <demin.han@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/vector_helper.c

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73..fe56c00 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -44,6 +44,7 @@
     target_ulong reserved = s2 &
                             MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
+    uint16_t vlen = cpu->cfg.vlenb << 3;
     int8_t lmul;
 
     if (vlmul & 4) {
@@ -53,10 +54,8 @@
          * VLEN * LMUL >= SEW
          * VLEN >> (8 - lmul) >= sew
          * (vlenb << 3) >> (8 - lmul) >= sew
-         * vlenb >> (8 - 3 - lmul) >= sew
          */
-        if (vlmul == 4 ||
-            cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
+        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
             vill = true;
         }
     }