commit | 938dd05ea1f3a9e3c713b1d73dc2992d62efb830 | [log] [tgz] |
---|---|---|
author | demin.han <demin.han@starfivetech.com> | Mon Feb 26 01:41:14 2024 +0800 |
committer | Alistair Francis <alistair.francis@wdc.com> | Fri Mar 08 20:48:03 2024 +1000 |
tree | 51534578d6023330daf4fc353dc8e78849815f4e | |
parent | a506c4289dd05b3134a1b6eb0b506eaee81e224d [diff] |
target/riscv: Fix shift count overflow The result of (8 - 3 - vlmul) is negative when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han <demin.han@starfivetech.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>