)]}'
{
  "commit": "92fd703df111300aeb905af7c24c0e4cde9a8a8a",
  "tree": "1f0274d5df5da984c55461970db87db7f349eacc",
  "parents": [
    "188f092144c6e750089f27d481d6efe2e3b46f60"
  ],
  "author": {
    "name": "Jamin Lin",
    "email": "jamin_lin@aspeedtech.com",
    "time": "Wed Oct 28 02:31:57 2026 +0000"
  },
  "committer": {
    "name": "Cédric Le Goater",
    "email": "clg@redhat.com",
    "time": "Sat Oct 31 06:52:18 2026 +0100"
  },
  "message": "hw/ssi/aspeed_smc: Fix AST2700 DMA flash address mask\n\nThe DMA flash address register (SPI084) holds the offset of the\nflash access within the controller\u0027s flash window. The AST2700 FMC,\nSPI0 and SPI1 controllers use a dma_flash_mask of 0x2FFFFFFC, which\nclears bit 28, and SPI2 uses 0x0FFFFFFC, which limits DMA to the\nfirst 256MB of the window.\n\nWith the default segment layout, FMC CS2 is mapped at offset\n0x10000000. A DMA read from that offset is masked to 0x0 and returns\ndata from CS0 instead of CS2.\n\nThe Linux driver programs SPI084 with the window offset masked by\n0x7fffffff, so bit 28 is a valid address bit.\n\nSet dma_flash_mask to 0x3FFFFFFC for all AST2700 controllers to cover\nthe full 1GB flash window.\n\nFixes: bdb3748dba30 (\"aspeed/smc: Add AST2700 support\")\nSigned-off-by: Jamin Lin \u003cjamin_lin@aspeedtech.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@oss.qualcomm.com\u003e\nReviewed-by: Cédric Le Goater \u003cclg@redhat.com\u003e\nLink: https://lore.kernel.org/qemu-devel/20261028023154.48395-3-jamin_lin@aspeedtech.com\nSigned-off-by: Cédric Le Goater \u003cclg@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "10ea9e5aa063f4716bbb7e58b3616c1c984c7cad",
      "old_mode": 33188,
      "old_path": "hw/ssi/aspeed_smc.c",
      "new_id": "c0c3666dbca3ac67b597e44041eade186c5b85a5",
      "new_mode": 33188,
      "new_path": "hw/ssi/aspeed_smc.c"
    }
  ]
}