commit 8ef23a329accd36394ffbddf87cc18ef0209dd6b
author Weiwei Li <liweiwei@iscas.ac.cn> Fri May 26 15:21:19 2023 +0800
committer Alistair Francis <alistair.francis@wdc.com> Tue Jun 13 17:33:28 2023 +1000
tree b856a1f3a96205eb9da251526aedf9eb77e8d8d2
parent bfc4f9e351e77c69fe21315815bc5db8ef7c22df

target/riscv: Introduce cur_insn_len into DisasContext

Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

target/riscv/translate.c

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6fbdb50..ea63d20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -61,6 +61,7 @@
     DisasContextBase base;
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
+    target_ulong cur_insn_len;
     target_ulong priv_ver;
     RISCVMXL misa_mxl_max;
     RISCVMXL xl;
@@ -1116,8 +1117,9 @@
     };
 
     ctx->virt_inst_excp = false;
+    ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
-    if (insn_len(opcode) == 2) {
+    if (ctx->cur_insn_len == 2) {
         ctx->opcode = opcode;
         ctx->pc_succ_insn = ctx->base.pc_next + 2;
         /*