)]}'
{
  "commit": "8d69fc2158edc83517622bd862beb29ffc6bbf02",
  "tree": "df9a18c1c3594659421068597beefffbea66a1b6",
  "parents": [
    "23fb57838ddfa9271f8ebf8b7a74ed7ba3359cd3"
  ],
  "author": {
    "name": "Zhao Liu",
    "email": "zhao1.liu@intel.com",
    "time": "Fri Jul 11 18:45:57 2025 +0800"
  },
  "committer": {
    "name": "Paolo Bonzini",
    "email": "pbonzini@redhat.com",
    "time": "Sat Jul 12 15:28:22 2025 +0200"
  },
  "message": "i386/cpu: Introduce cache model for SapphireRapids\n\nAdd the cache model to SapphireRapids (v4) to better emulate its\nenvironment.\n\nThe cache model is based on SapphireRapids-SP (Scalable Performance):\n\n      --- cache 0 ---\n      cache type                         \u003d data cache (1)\n      cache level                        \u003d 0x1 (1)\n      self-initializing cache level      \u003d true\n      fully associative cache            \u003d false\n      maximum IDs for CPUs sharing cache \u003d 0x1 (1)\n      maximum IDs for cores in pkg       \u003d 0x3f (63)\n      system coherency line size         \u003d 0x40 (64)\n      physical line partitions           \u003d 0x1 (1)\n      ways of associativity              \u003d 0xc (12)\n      number of sets                     \u003d 0x40 (64)\n      WBINVD/INVD acts on lower caches   \u003d false\n      inclusive to lower caches          \u003d false\n      complex cache indexing             \u003d false\n      number of sets (s)                 \u003d 64\n      (size synth)                       \u003d 49152 (48 KB)\n      --- cache 1 ---\n      cache type                         \u003d instruction cache (2)\n      cache level                        \u003d 0x1 (1)\n      self-initializing cache level      \u003d true\n      fully associative cache            \u003d false\n      maximum IDs for CPUs sharing cache \u003d 0x1 (1)\n      maximum IDs for cores in pkg       \u003d 0x3f (63)\n      system coherency line size         \u003d 0x40 (64)\n      physical line partitions           \u003d 0x1 (1)\n      ways of associativity              \u003d 0x8 (8)\n      number of sets                     \u003d 0x40 (64)\n      WBINVD/INVD acts on lower caches   \u003d false\n      inclusive to lower caches          \u003d false\n      complex cache indexing             \u003d false\n      number of sets (s)                 \u003d 64\n      (size synth)                       \u003d 32768 (32 KB)\n      --- cache 2 ---\n      cache type                         \u003d unified cache (3)\n      cache level                        \u003d 0x2 (2)\n      self-initializing cache level      \u003d true\n      fully associative cache            \u003d false\n      maximum IDs for CPUs sharing cache \u003d 0x1 (1)\n      maximum IDs for cores in pkg       \u003d 0x3f (63)\n      system coherency line size         \u003d 0x40 (64)\n      physical line partitions           \u003d 0x1 (1)\n      ways of associativity              \u003d 0x10 (16)\n      number of sets                     \u003d 0x800 (2048)\n      WBINVD/INVD acts on lower caches   \u003d false\n      inclusive to lower caches          \u003d false\n      complex cache indexing             \u003d false\n      number of sets (s)                 \u003d 2048\n      (size synth)                       \u003d 2097152 (2 MB)\n      --- cache 3 ---\n      cache type                         \u003d unified cache (3)\n      cache level                        \u003d 0x3 (3)\n      self-initializing cache level      \u003d true\n      fully associative cache            \u003d false\n      maximum IDs for CPUs sharing cache \u003d 0x7f (127)\n      maximum IDs for cores in pkg       \u003d 0x3f (63)\n      system coherency line size         \u003d 0x40 (64)\n      physical line partitions           \u003d 0x1 (1)\n      ways of associativity              \u003d 0xf (15)\n      number of sets                     \u003d 0x10000 (65536)\n      WBINVD/INVD acts on lower caches   \u003d false\n      inclusive to lower caches          \u003d false\n      complex cache indexing             \u003d true\n      number of sets (s)                 \u003d 65536\n      (size synth)                       \u003d 62914560 (60 MB)\n      --- cache 4 ---\n      cache type                         \u003d no more caches (0)\n\nSuggested-by: Tejus GK \u003ctejus.gk@nutanix.com\u003e\nSuggested-by: Jason Zeng \u003cjason.zeng@intel.com\u003e\nSuggested-by: \"Daniel P . Berrangé\" \u003cberrange@redhat.com\u003e\nReviewed-by: Dapeng Mi \u003cdapeng1.mi@linux.intel.com\u003e\nReviewed-by: Tao Su \u003ctao1.su@linux.intel.com\u003e\nTested-by: Yi Lai \u003cyi1.lai@intel.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nLink: https://lore.kernel.org/r/20250711104603.1634832-4-zhao1.liu@intel.com\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d1fc74eb0e396e17a82d50bf1f004fefa1608457",
      "old_mode": 33188,
      "old_path": "target/i386/cpu.c",
      "new_id": "b3b29f69666a22c81d7590f6e504e4804d8f5a8a",
      "new_mode": 33188,
      "new_path": "target/i386/cpu.c"
    }
  ]
}