target/riscv: Allow generating hlv/hlvx/hsv instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bdd8563..84080dd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -78,6 +78,7 @@
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -223,6 +224,16 @@
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
# *** RV32H Base Instruction Set ***
+hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
+hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
+hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
+hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
+hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
+hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
+hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
+hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
+hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
+hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
