)]}'
{
  "commit": "895d4367d6d8afca49c2d7ed6c9e95e853e72e7f",
  "tree": "17696e1afab90e17dd0e242e9aab34135fcaf403",
  "parents": [
    "e69bddfc75bdc01f23786a26836bd351702507d7"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 18 18:40:14 2026 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 18 18:40:14 2026 +0000"
  },
  "message": "target/arm/tcg: Use \"or SME\" feature checks where needed\n\nMany SVE instructions should be provided where the CPU implements\neither SVE or SME. Currently we largely check only for features\naa64_sve or aa64_sve2. This happens to work because we forbid\ncreation of a CPU with SME but not SVE. To allow users to create\nSME-only CPUs we need to update the conditions to use the \"or SME\"\nversions of the feature tests instead.\n\nThis commit was created by going through translate-sve.c from\ntop to bottom looking for aa64_sve feature tests and cross\nchecking those against the instruction descriptions in the Arm ARM,\nwhich will say \"(FEAT_SVE || FEAT_SME)\" for instructions that\nare provided for both features, and \"(FEAT_SME)\" for the rarer\ninstructions that are SME only.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20260202133353.2231685-11-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fe59126d2b46fa962481a5711b782d24c290be5f",
      "old_mode": 33188,
      "old_path": "target/arm/tcg/translate-sve.c",
      "new_id": "44eda7b07d8a6535dcd686e414fa5b7505b08b02",
      "new_mode": 33188,
      "new_path": "target/arm/tcg/translate-sve.c"
    }
  ]
}