tree d6ff1489fd56e8fc9c586661014eeec74a634f96
parent 6b8a05373bf142fe5fd3839c3675da005bfc9b49
author Nicholas Piggin <npiggin@gmail.com> 1687266641 +1000
committer Cédric Le Goater <clg@kaod.org> 1687725690 +0200

target/ppc: Fix instruction loading endianness in alignment interrupt

powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>