)]}'
{
  "commit": "8676007eff04bb4e454bcdf92fab3f855bcc59b3",
  "tree": "4867b8a42fe637decb96eb413c8abcd8c9bfe5ac",
  "parents": [
    "c4d16d4168862735d746dd5d9e579cfc45c5e123"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue Sep 17 17:13:37 2024 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Sep 19 13:17:21 2024 +0100"
  },
  "message": "target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1\n\nThe Neoverse-V1 TRM is a bit confused about the layout of the\nID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value\nfor this ID register.  Trust instead section 3.2.74\u0027s list of which\nfields are set.\n\nThis means that we stop incorrectly reporting FEAT_XS as present, and\nnow report the presence of FEAT_BF16.\n\nCc: qemu-stable@nongnu.org\nReported-by: Marcin Juszkiewicz \u003cmarcin.juszkiewicz@linaro.org\u003e\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20240917161337.3012188-1-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b9f34f044d0b95c2b93958f7c90ce07b96fd9fb2",
      "old_mode": 33188,
      "old_path": "target/arm/tcg/cpu64.c",
      "new_id": "0168920828651492b1114d66ab0fc72c20dda2a8",
      "new_mode": 33188,
      "new_path": "target/arm/tcg/cpu64.c"
    }
  ]
}