Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* i386: fix issue with cache topology passthrough
* scsi-disk: migrate emulated requests
* i386/sev: fix Coverity issues
* i386/tcg: more conversions to new decoder
# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmZv6kMUHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroOn4Af/evnpsae1fm8may1NQmmezKiks/4X
# cR0GaQ7w75Oas05jKsG7Xnrq3Vn6p5wllf3Wf00p7F1iJX18azY9rQgIsUVUgVem
# /EIZk1eM6+mDxuIG0taPxc5Aw3cfIBWAjUmzsXrSr55e/wyiIxZCeUo2zk8Il+iL
# Z4ceNzY5PZzc2Fl10D3cGs/+ynfiDM53ucwe3ve2T6NrxEVfKQPp5jkIUkBUba6z
# zM5O4Q5KTEZYVth1gbDTB/uUJLUFjQ12kCQfRCNX+bEPDHwARr0UWr/Oxtz0jZSd
# FvXohz7tI+v+ph0xHyE4tEFqryvLCII1td2ohTAYZZXNGkjK6XZildngBw==
# =m4BE
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 17 Jun 2024 12:48:19 AM PDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (25 commits)
target/i386: SEV: do not assume machine->cgs is SEV
target/i386: convert CMPXCHG to new decoder
target/i386: convert XADD to new decoder
target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT to new decoder
target/i386: convert SHLD/SHRD to new decoder
target/i386: adapt gen_shift_count for SHLD/SHRD
target/i386: pull load/writeback out of gen_shiftd_rm_T1
target/i386: convert non-grouped, helper-based 2-byte opcodes
target/i386: split X86_CHECK_prot into PE and VM86 checks
target/i386: finish converting 0F AE to the new decoder
target/i386: fix bad sorting of entries in the 0F table
target/i386: replace read_crN helper with read_cr8
target/i386: convert MOV from/to CR and DR to new decoder
target/i386: fix processing of intercept 0 (read CR0)
target/i386: replace NoSeg special with NoLoadEA
target/i386: change X86_ENTRYwr to use T0, use it for moves
target/i386: change X86_ENTRYr to use T0
target/i386: put BLS* input in T1, use generic flag writeback
target/i386: rewrite flags writeback for ADCX/ADOX
target/i386: remove CPUX86State argument from generator functions
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 9515562..0f63bcd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1158,6 +1158,9 @@
ASPEED BMCs
M: Cédric Le Goater <clg@kaod.org>
M: Peter Maydell <peter.maydell@linaro.org>
+R: Steven Lee <steven_lee@aspeedtech.com>
+R: Troy Lee <leetroy@gmail.com>
+R: Jamin Lin <jamin_lin@aspeedtech.com>
R: Andrew Jeffery <andrew@codeconstruct.com.au>
R: Joel Stanley <joel@jms.id.au>
L: qemu-arm@nongnu.org
diff --git a/backends/tpm/tpm_util.c b/backends/tpm/tpm_util.c
index 1856589..cf13855 100644
--- a/backends/tpm/tpm_util.c
+++ b/backends/tpm/tpm_util.c
@@ -339,10 +339,11 @@
size_t len, i;
char *line_buffer, *p;
- if (!trace_event_get_state_backends(TRACE_TPM_UTIL_SHOW_BUFFER)) {
+ if (!trace_event_get_state_backends(TRACE_TPM_UTIL_SHOW_BUFFER_CONTENT)) {
return;
}
len = MIN(tpm_cmd_get_size(buffer), buffer_size);
+ trace_tpm_util_show_buffer_header(string, len);
/*
* allocate enough room for 3 chars per buffer entry plus a
@@ -356,7 +357,7 @@
}
p += sprintf(p, "%.2X ", buffer[i]);
}
- trace_tpm_util_show_buffer(string, len, line_buffer);
+ trace_tpm_util_show_buffer_content(line_buffer);
g_free(line_buffer);
}
diff --git a/backends/tpm/trace-events b/backends/tpm/trace-events
index 1ecef42..cb5cfa6 100644
--- a/backends/tpm/trace-events
+++ b/backends/tpm/trace-events
@@ -10,7 +10,8 @@
tpm_util_get_buffer_size_hdr_len2(uint32_t len, size_t expected) "tpm2_resp->hdr.len = %u, expected = %zu"
tpm_util_get_buffer_size_len2(uint32_t len, size_t expected) "tpm2_resp->len = %u, expected = %zu"
tpm_util_get_buffer_size(size_t len) "buffersize of device: %zu"
-tpm_util_show_buffer(const char *direction, size_t len, const char *buf) "direction: %s len: %zu\n%s"
+tpm_util_show_buffer_header(const char *direction, size_t len) "direction: %s len: %zu"
+tpm_util_show_buffer_content(const char *buf) "%s"
# tpm_emulator.c
tpm_emulator_set_locality(uint8_t locty) "setting locality to %d"
diff --git a/block/copy-before-write.c b/block/copy-before-write.c
index cd65524..853e01a 100644
--- a/block/copy-before-write.c
+++ b/block/copy-before-write.c
@@ -43,7 +43,7 @@
BlockCopyState *bcs;
BdrvChild *target;
OnCbwError on_cbw_error;
- uint32_t cbw_timeout_ns;
+ uint64_t cbw_timeout_ns;
bool discard_source;
/*
diff --git a/block/crypto.c b/block/crypto.c
index 21eed90..4eed3ff 100644
--- a/block/crypto.c
+++ b/block/crypto.c
@@ -363,7 +363,6 @@
block_crypto_read_func,
bs,
cflags,
- 1,
errp);
if (!crypto->block) {
diff --git a/block/file-posix.c b/block/file-posix.c
index 35684f7..be25e35 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -159,6 +159,7 @@
bool has_discard:1;
bool has_write_zeroes:1;
bool use_linux_aio:1;
+ bool has_laio_fdsync:1;
bool use_linux_io_uring:1;
int page_cache_inconsistent; /* errno from fdatasync failure */
bool has_fallocate;
@@ -718,6 +719,9 @@
ret = -EINVAL;
goto fail;
}
+ if (s->use_linux_aio) {
+ s->has_laio_fdsync = laio_has_fdsync(s->fd);
+ }
#else
if (s->use_linux_aio) {
error_setg(errp, "aio=native was specified, but is not supported "
@@ -1039,8 +1043,7 @@
}
static int raw_reconfigure_getfd(BlockDriverState *bs, int flags,
- int *open_flags, uint64_t perm, bool force_dup,
- Error **errp)
+ int *open_flags, uint64_t perm, Error **errp)
{
BDRVRawState *s = bs->opaque;
int fd = -1;
@@ -1068,7 +1071,7 @@
assert((s->open_flags & O_ASYNC) == 0);
#endif
- if (!force_dup && *open_flags == s->open_flags) {
+ if (*open_flags == s->open_flags) {
/* We're lucky, the existing fd is fine */
return s->fd;
}
@@ -2600,6 +2603,11 @@
return luring_co_submit(bs, s->fd, 0, NULL, QEMU_AIO_FLUSH);
}
#endif
+#ifdef CONFIG_LINUX_AIO
+ if (s->has_laio_fdsync && raw_check_linux_aio(s)) {
+ return laio_co_submit(s->fd, 0, NULL, QEMU_AIO_FLUSH, 0);
+ }
+#endif
return raw_thread_pool_submit(handle_aiocb_flush, &acb);
}
@@ -3748,8 +3756,7 @@
int ret;
/* We may need a new fd if auto-read-only switches the mode */
- ret = raw_reconfigure_getfd(bs, input_flags, &open_flags, perm,
- false, errp);
+ ret = raw_reconfigure_getfd(bs, input_flags, &open_flags, perm, errp);
if (ret < 0) {
return ret;
} else if (ret != s->fd) {
diff --git a/block/linux-aio.c b/block/linux-aio.c
index ec05d94..e3b5ec9 100644
--- a/block/linux-aio.c
+++ b/block/linux-aio.c
@@ -384,6 +384,9 @@
case QEMU_AIO_READ:
io_prep_preadv(iocbs, fd, qiov->iov, qiov->niov, offset);
break;
+ case QEMU_AIO_FLUSH:
+ io_prep_fdsync(iocbs, fd);
+ break;
/* Currently Linux kernel does not support other operations */
default:
fprintf(stderr, "%s: invalid AIO request type 0x%x.\n",
@@ -412,7 +415,7 @@
AioContext *ctx = qemu_get_current_aio_context();
struct qemu_laiocb laiocb = {
.co = qemu_coroutine_self(),
- .nbytes = qiov->size,
+ .nbytes = qiov ? qiov->size : 0,
.ctx = aio_get_linux_aio(ctx),
.ret = -EINPROGRESS,
.is_read = (type == QEMU_AIO_READ),
@@ -486,3 +489,19 @@
}
g_free(s);
}
+
+bool laio_has_fdsync(int fd)
+{
+ struct iocb cb;
+ struct iocb *cbs[] = {&cb, NULL};
+
+ io_context_t ctx = 0;
+ io_setup(1, &ctx);
+
+ /* check if host kernel supports IO_CMD_FDSYNC */
+ io_prep_fdsync(&cb, fd);
+ int ret = io_submit(ctx, 1, cbs);
+
+ io_destroy(ctx);
+ return (ret == -EINVAL) ? false : true;
+}
diff --git a/block/qcow.c b/block/qcow.c
index ca8e1d5..c2f89db 100644
--- a/block/qcow.c
+++ b/block/qcow.c
@@ -211,7 +211,7 @@
cflags |= QCRYPTO_BLOCK_OPEN_NO_IO;
}
s->crypto = qcrypto_block_open(crypto_opts, "encrypt.",
- NULL, NULL, cflags, 1, errp);
+ NULL, NULL, cflags, errp);
if (!s->crypto) {
ret = -EINVAL;
goto fail;
diff --git a/block/qcow2.c b/block/qcow2.c
index 956128b..10883a2 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -321,7 +321,7 @@
}
s->crypto = qcrypto_block_open(s->crypto_opts, "encrypt.",
qcow2_crypto_hdr_read_func,
- bs, cflags, QCOW2_MAX_THREADS, errp);
+ bs, cflags, errp);
if (!s->crypto) {
return -EINVAL;
}
@@ -1701,8 +1701,7 @@
cflags |= QCRYPTO_BLOCK_OPEN_NO_IO;
}
s->crypto = qcrypto_block_open(s->crypto_opts, "encrypt.",
- NULL, NULL, cflags,
- QCOW2_MAX_THREADS, errp);
+ NULL, NULL, cflags, errp);
if (!s->crypto) {
ret = -EINVAL;
goto fail;
diff --git a/crypto/block-luks.c b/crypto/block-luks.c
index 3ee928f..5b777c1 100644
--- a/crypto/block-luks.c
+++ b/crypto/block-luks.c
@@ -1189,7 +1189,6 @@
QCryptoBlockReadFunc readfunc,
void *opaque,
unsigned int flags,
- size_t n_threads,
Error **errp)
{
QCryptoBlockLUKS *luks = NULL;
@@ -1262,7 +1261,6 @@
luks->cipher_mode,
masterkey,
luks->header.master_key_len,
- n_threads,
errp) < 0) {
goto fail;
}
@@ -1456,7 +1454,7 @@
/* Setup the block device payload encryption objects */
if (qcrypto_block_init_cipher(block, luks_opts.cipher_alg,
luks_opts.cipher_mode, masterkey,
- luks->header.master_key_len, 1, errp) < 0) {
+ luks->header.master_key_len, errp) < 0) {
goto error;
}
diff --git a/crypto/block-qcow.c b/crypto/block-qcow.c
index 4d7cf36..42e9556 100644
--- a/crypto/block-qcow.c
+++ b/crypto/block-qcow.c
@@ -44,7 +44,6 @@
static int
qcrypto_block_qcow_init(QCryptoBlock *block,
const char *keysecret,
- size_t n_threads,
Error **errp)
{
char *password;
@@ -75,7 +74,7 @@
ret = qcrypto_block_init_cipher(block, QCRYPTO_CIPHER_ALG_AES_128,
QCRYPTO_CIPHER_MODE_CBC,
keybuf, G_N_ELEMENTS(keybuf),
- n_threads, errp);
+ errp);
if (ret < 0) {
ret = -ENOTSUP;
goto fail;
@@ -100,7 +99,6 @@
QCryptoBlockReadFunc readfunc G_GNUC_UNUSED,
void *opaque G_GNUC_UNUSED,
unsigned int flags,
- size_t n_threads,
Error **errp)
{
if (flags & QCRYPTO_BLOCK_OPEN_NO_IO) {
@@ -115,7 +113,7 @@
return -1;
}
return qcrypto_block_qcow_init(block, options->u.qcow.key_secret,
- n_threads, errp);
+ errp);
}
}
@@ -135,7 +133,7 @@
return -1;
}
/* QCow2 has no special header, since everything is hardwired */
- return qcrypto_block_qcow_init(block, options->u.qcow.key_secret, 1, errp);
+ return qcrypto_block_qcow_init(block, options->u.qcow.key_secret, errp);
}
diff --git a/crypto/block.c b/crypto/block.c
index 506ea1d..3bcc427 100644
--- a/crypto/block.c
+++ b/crypto/block.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "qemu/lockable.h"
#include "blockpriv.h"
#include "block-qcow.h"
#include "block-luks.h"
@@ -52,11 +53,12 @@
QCryptoBlockReadFunc readfunc,
void *opaque,
unsigned int flags,
- size_t n_threads,
Error **errp)
{
QCryptoBlock *block = g_new0(QCryptoBlock, 1);
+ qemu_mutex_init(&block->mutex);
+
block->format = options->format;
if (options->format >= G_N_ELEMENTS(qcrypto_block_drivers) ||
@@ -70,14 +72,12 @@
block->driver = qcrypto_block_drivers[options->format];
if (block->driver->open(block, options, optprefix,
- readfunc, opaque, flags, n_threads, errp) < 0)
+ readfunc, opaque, flags, errp) < 0)
{
g_free(block);
return NULL;
}
- qemu_mutex_init(&block->mutex);
-
return block;
}
@@ -92,6 +92,8 @@
{
QCryptoBlock *block = g_new0(QCryptoBlock, 1);
+ qemu_mutex_init(&block->mutex);
+
block->format = options->format;
if (options->format >= G_N_ELEMENTS(qcrypto_block_drivers) ||
@@ -111,8 +113,6 @@
return NULL;
}
- qemu_mutex_init(&block->mutex);
-
return block;
}
@@ -227,37 +227,42 @@
* This function is used only in test with one thread (it's safe to skip
* pop/push interface), so it's enough to assert it here:
*/
- assert(block->n_ciphers <= 1);
- return block->ciphers ? block->ciphers[0] : NULL;
+ assert(block->max_free_ciphers <= 1);
+ return block->free_ciphers ? block->free_ciphers[0] : NULL;
}
-static QCryptoCipher *qcrypto_block_pop_cipher(QCryptoBlock *block)
+static QCryptoCipher *qcrypto_block_pop_cipher(QCryptoBlock *block,
+ Error **errp)
{
- QCryptoCipher *cipher;
+ /* Usually there is a free cipher available */
+ WITH_QEMU_LOCK_GUARD(&block->mutex) {
+ if (block->n_free_ciphers > 0) {
+ block->n_free_ciphers--;
+ return block->free_ciphers[block->n_free_ciphers];
+ }
+ }
- qemu_mutex_lock(&block->mutex);
-
- assert(block->n_free_ciphers > 0);
- block->n_free_ciphers--;
- cipher = block->ciphers[block->n_free_ciphers];
-
- qemu_mutex_unlock(&block->mutex);
-
- return cipher;
+ /* Otherwise allocate a new cipher */
+ return qcrypto_cipher_new(block->alg, block->mode, block->key,
+ block->nkey, errp);
}
static void qcrypto_block_push_cipher(QCryptoBlock *block,
QCryptoCipher *cipher)
{
- qemu_mutex_lock(&block->mutex);
+ QEMU_LOCK_GUARD(&block->mutex);
- assert(block->n_free_ciphers < block->n_ciphers);
- block->ciphers[block->n_free_ciphers] = cipher;
+ if (block->n_free_ciphers == block->max_free_ciphers) {
+ block->max_free_ciphers++;
+ block->free_ciphers = g_renew(QCryptoCipher *,
+ block->free_ciphers,
+ block->max_free_ciphers);
+ }
+
+ block->free_ciphers[block->n_free_ciphers] = cipher;
block->n_free_ciphers++;
-
- qemu_mutex_unlock(&block->mutex);
}
@@ -265,24 +270,31 @@
QCryptoCipherAlgorithm alg,
QCryptoCipherMode mode,
const uint8_t *key, size_t nkey,
- size_t n_threads, Error **errp)
+ Error **errp)
{
- size_t i;
+ QCryptoCipher *cipher;
- assert(!block->ciphers && !block->n_ciphers && !block->n_free_ciphers);
+ assert(!block->free_ciphers && !block->max_free_ciphers &&
+ !block->n_free_ciphers);
- block->ciphers = g_new0(QCryptoCipher *, n_threads);
+ /* Stash away cipher parameters for qcrypto_block_pop_cipher() */
+ block->alg = alg;
+ block->mode = mode;
+ block->key = g_memdup2(key, nkey);
+ block->nkey = nkey;
- for (i = 0; i < n_threads; i++) {
- block->ciphers[i] = qcrypto_cipher_new(alg, mode, key, nkey, errp);
- if (!block->ciphers[i]) {
- qcrypto_block_free_cipher(block);
- return -1;
- }
- block->n_ciphers++;
- block->n_free_ciphers++;
+ /*
+ * Create a new cipher to validate the parameters now. This reduces the
+ * chance of cipher creation failing at I/O time.
+ */
+ cipher = qcrypto_block_pop_cipher(block, errp);
+ if (!cipher) {
+ g_free(block->key);
+ block->key = NULL;
+ return -1;
}
+ qcrypto_block_push_cipher(block, cipher);
return 0;
}
@@ -291,19 +303,23 @@
{
size_t i;
- if (!block->ciphers) {
+ g_free(block->key);
+ block->key = NULL;
+
+ if (!block->free_ciphers) {
return;
}
- assert(block->n_ciphers == block->n_free_ciphers);
+ /* All popped ciphers were eventually pushed back */
+ assert(block->n_free_ciphers == block->max_free_ciphers);
- for (i = 0; i < block->n_ciphers; i++) {
- qcrypto_cipher_free(block->ciphers[i]);
+ for (i = 0; i < block->max_free_ciphers; i++) {
+ qcrypto_cipher_free(block->free_ciphers[i]);
}
- g_free(block->ciphers);
- block->ciphers = NULL;
- block->n_ciphers = block->n_free_ciphers = 0;
+ g_free(block->free_ciphers);
+ block->free_ciphers = NULL;
+ block->max_free_ciphers = block->n_free_ciphers = 0;
}
QCryptoIVGen *qcrypto_block_get_ivgen(QCryptoBlock *block)
@@ -311,7 +327,7 @@
/* ivgen should be accessed under mutex. However, this function is used only
* in test with one thread, so it's enough to assert it here:
*/
- assert(block->n_ciphers <= 1);
+ assert(block->max_free_ciphers <= 1);
return block->ivgen;
}
@@ -446,7 +462,10 @@
Error **errp)
{
int ret;
- QCryptoCipher *cipher = qcrypto_block_pop_cipher(block);
+ QCryptoCipher *cipher = qcrypto_block_pop_cipher(block, errp);
+ if (!cipher) {
+ return -1;
+ }
ret = do_qcrypto_block_cipher_encdec(cipher, block->niv, block->ivgen,
&block->mutex, sectorsize, offset, buf,
@@ -465,7 +484,10 @@
Error **errp)
{
int ret;
- QCryptoCipher *cipher = qcrypto_block_pop_cipher(block);
+ QCryptoCipher *cipher = qcrypto_block_pop_cipher(block, errp);
+ if (!cipher) {
+ return -1;
+ }
ret = do_qcrypto_block_cipher_encdec(cipher, block->niv, block->ivgen,
&block->mutex, sectorsize, offset, buf,
diff --git a/crypto/blockpriv.h b/crypto/blockpriv.h
index 836f3b4..b8f77cb 100644
--- a/crypto/blockpriv.h
+++ b/crypto/blockpriv.h
@@ -32,8 +32,14 @@
const QCryptoBlockDriver *driver;
void *opaque;
- QCryptoCipher **ciphers;
- size_t n_ciphers;
+ /* Cipher parameters */
+ QCryptoCipherAlgorithm alg;
+ QCryptoCipherMode mode;
+ uint8_t *key;
+ size_t nkey;
+
+ QCryptoCipher **free_ciphers;
+ size_t max_free_ciphers;
size_t n_free_ciphers;
QCryptoIVGen *ivgen;
QemuMutex mutex;
@@ -53,7 +59,6 @@
QCryptoBlockReadFunc readfunc,
void *opaque,
unsigned int flags,
- size_t n_threads,
Error **errp);
int (*create)(QCryptoBlock *block,
@@ -130,7 +135,7 @@
QCryptoCipherAlgorithm alg,
QCryptoCipherMode mode,
const uint8_t *key, size_t nkey,
- size_t n_threads, Error **errp);
+ Error **errp);
void qcrypto_block_free_cipher(QCryptoBlock *block);
diff --git a/docs/devel/migration/features.rst b/docs/devel/migration/features.rst
index d5ca7b8..58f8fd9 100644
--- a/docs/devel/migration/features.rst
+++ b/docs/devel/migration/features.rst
@@ -12,3 +12,5 @@
virtio
mapped-ram
CPR
+ qpl-compression
+ uadk-compression
diff --git a/docs/devel/migration/qpl-compression.rst b/docs/devel/migration/qpl-compression.rst
new file mode 100644
index 0000000..990992d
--- /dev/null
+++ b/docs/devel/migration/qpl-compression.rst
@@ -0,0 +1,260 @@
+===============
+QPL Compression
+===============
+The Intel Query Processing Library (Intel ``QPL``) is an open-source library to
+provide compression and decompression features and it is based on deflate
+compression algorithm (RFC 1951).
+
+The ``QPL`` compression relies on Intel In-Memory Analytics Accelerator(``IAA``)
+and Shared Virtual Memory(``SVM``) technology, they are new features supported
+from Intel 4th Gen Intel Xeon Scalable processors, codenamed Sapphire Rapids
+processor(``SPR``).
+
+For more ``QPL`` introduction, please refer to `QPL Introduction
+<https://intel.github.io/qpl/documentation/introduction_docs/introduction.html>`_
+
+QPL Compression Framework
+=========================
+
+::
+
+ +----------------+ +------------------+
+ | MultiFD Thread | |accel-config tool |
+ +-------+--------+ +--------+---------+
+ | |
+ | |
+ |compress/decompress |
+ +-------+--------+ | Setup IAA
+ | QPL library | | Resources
+ +-------+---+----+ |
+ | | |
+ | +-------------+-------+
+ | Open IAA |
+ | Devices +-----+-----+
+ | |idxd driver|
+ | +-----+-----+
+ | |
+ | |
+ | +-----+-----+
+ +-----------+IAA Devices|
+ Submit jobs +-----------+
+ via enqcmd
+
+
+QPL Build And Installation
+--------------------------
+
+.. code-block:: shell
+
+ $git clone --recursive https://github.com/intel/qpl.git qpl
+ $mkdir qpl/build
+ $cd qpl/build
+ $cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr -DQPL_LIBRARY_TYPE=SHARED ..
+ $sudo cmake --build . --target install
+
+For more details about ``QPL`` installation, please refer to `QPL Installation
+<https://intel.github.io/qpl/documentation/get_started_docs/installation.html>`_
+
+IAA Device Management
+---------------------
+
+The number of ``IAA`` devices will vary depending on the Xeon product model.
+On a ``SPR`` server, there can be a maximum of 8 ``IAA`` devices, with up to
+4 devices per socket.
+
+By default, all ``IAA`` devices are disabled and need to be configured and
+enabled by users manually.
+
+Check the number of devices through the following command
+
+.. code-block:: shell
+
+ #lspci -d 8086:0cfe
+ 6a:02.0 System peripheral: Intel Corporation Device 0cfe
+ 6f:02.0 System peripheral: Intel Corporation Device 0cfe
+ 74:02.0 System peripheral: Intel Corporation Device 0cfe
+ 79:02.0 System peripheral: Intel Corporation Device 0cfe
+ e7:02.0 System peripheral: Intel Corporation Device 0cfe
+ ec:02.0 System peripheral: Intel Corporation Device 0cfe
+ f1:02.0 System peripheral: Intel Corporation Device 0cfe
+ f6:02.0 System peripheral: Intel Corporation Device 0cfe
+
+IAA Device Configuration And Enabling
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The ``accel-config`` tool is used to enable ``IAA`` devices and configure
+``IAA`` hardware resources(work queues and engines). One ``IAA`` device
+has 8 work queues and 8 processing engines, multiple engines can be assigned
+to a work queue via ``group`` attribute.
+
+For ``accel-config`` installation, please refer to `accel-config installation
+<https://github.com/intel/idxd-config>`_
+
+One example of configuring and enabling an ``IAA`` device.
+
+.. code-block:: shell
+
+ #accel-config config-engine iax1/engine1.0 -g 0
+ #accel-config config-engine iax1/engine1.1 -g 0
+ #accel-config config-engine iax1/engine1.2 -g 0
+ #accel-config config-engine iax1/engine1.3 -g 0
+ #accel-config config-engine iax1/engine1.4 -g 0
+ #accel-config config-engine iax1/engine1.5 -g 0
+ #accel-config config-engine iax1/engine1.6 -g 0
+ #accel-config config-engine iax1/engine1.7 -g 0
+ #accel-config config-wq iax1/wq1.0 -g 0 -s 128 -p 10 -b 1 -t 128 -m shared -y user -n app1 -d user
+ #accel-config enable-device iax1
+ #accel-config enable-wq iax1/wq1.0
+
+.. note::
+ IAX is an early name for IAA
+
+- The ``IAA`` device index is 1, use ``ls -lh /sys/bus/dsa/devices/iax*``
+ command to query the ``IAA`` device index.
+
+- 8 engines and 1 work queue are configured in group 0, so all compression jobs
+ submitted to this work queue can be processed by all engines at the same time.
+
+- Set work queue attributes including the work mode, work queue size and so on.
+
+- Enable the ``IAA1`` device and work queue 1.0
+
+.. note::
+
+ Set work queue mode to shared mode, since ``QPL`` library only supports
+ shared mode
+
+For more detailed configuration, please refer to `IAA Configuration Samples
+<https://github.com/intel/idxd-config/tree/stable/Documentation/accfg>`_
+
+IAA Unit Test
+^^^^^^^^^^^^^
+
+- Enabling ``IAA`` devices for Xeon platform, please refer to `IAA User Guide
+ <https://www.intel.com/content/www/us/en/content-details/780887/intel-in-memory-analytics-accelerator-intel-iaa.html>`_
+
+- ``IAA`` device driver is Intel Data Accelerator Driver (idxd), it is
+ recommended that the minimum version of Linux kernel is 5.18.
+
+- Add ``"intel_iommu=on,sm_on"`` parameter to kernel command line
+ for ``SVM`` feature enabling.
+
+Here is an easy way to verify ``IAA`` device driver and ``SVM`` with `iaa_test
+<https://github.com/intel/idxd-config/tree/stable/test>`_
+
+.. code-block:: shell
+
+ #./test/iaa_test
+ [ info] alloc wq 0 shared size 128 addr 0x7f26cebe5000 batch sz 0xfffffffe xfer sz 0x80000000
+ [ info] test noop: tflags 0x1 num_desc 1
+ [ info] preparing descriptor for noop
+ [ info] Submitted all noop jobs
+ [ info] verifying task result for 0x16f7e20
+ [ info] test with op 0 passed
+
+
+IAA Resources Allocation For Migration
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+There is no ``IAA`` resource configuration parameters for migration and
+``accel-config`` tool configuration cannot directly specify the ``IAA``
+resources used for migration.
+
+The multifd migration with ``QPL`` compression method will use all work
+queues that are enabled and shared mode.
+
+.. note::
+
+ Accessing IAA resources requires ``sudo`` command or ``root`` privileges
+ by default. Administrators can modify the IAA device node ownership
+ so that QEMU can use IAA with specified user permissions.
+
+ For example
+
+ #chown -R qemu /dev/iax
+
+Shared Virtual Memory(SVM) Introduction
+=======================================
+
+An ability for an accelerator I/O device to operate in the same virtual
+memory space of applications on host processors. It also implies the
+ability to operate from pageable memory, avoiding functional requirements
+to pin memory for DMA operations.
+
+When using ``SVM`` technology, users do not need to reserve memory for the
+``IAA`` device and perform pin memory operation. The ``IAA`` device can
+directly access data using the virtual address of the process.
+
+For more ``SVM`` technology, please refer to
+`Shared Virtual Addressing (SVA) with ENQCMD
+<https://docs.kernel.org/next/x86/sva.html>`_
+
+
+How To Use QPL Compression In Migration
+=======================================
+
+1 - Installation of ``QPL`` library and ``accel-config`` library if using IAA
+
+2 - Configure and enable ``IAA`` devices and work queues via ``accel-config``
+
+3 - Build ``QEMU`` with ``--enable-qpl`` parameter
+
+ E.g. configure --target-list=x86_64-softmmu --enable-kvm ``--enable-qpl``
+
+4 - Enable ``QPL`` compression during migration
+
+ Set ``migrate_set_parameter multifd-compression qpl`` when migrating, the
+ ``QPL`` compression does not support configuring the compression level, it
+ only supports one compression level.
+
+The Difference Between QPL And ZLIB
+===================================
+
+Although both ``QPL`` and ``ZLIB`` are based on the deflate compression
+algorithm, and ``QPL`` can support the header and tail of ``ZLIB``, ``QPL``
+is still not fully compatible with the ``ZLIB`` compression in the migration.
+
+``QPL`` only supports 4K history buffer, and ``ZLIB`` is 32K by default.
+``ZLIB`` compresses data that ``QPL`` may not decompress correctly and
+vice versa.
+
+``QPL`` does not support the ``Z_SYNC_FLUSH`` operation in ``ZLIB`` streaming
+compression, current ``ZLIB`` implementation uses ``Z_SYNC_FLUSH``, so each
+``multifd`` thread has a ``ZLIB`` streaming context, and all page compression
+and decompression are based on this stream. ``QPL`` cannot decompress such data
+and vice versa.
+
+The introduction for ``Z_SYNC_FLUSH``, please refer to `Zlib Manual
+<https://www.zlib.net/manual.html>`_
+
+The Best Practices
+==================
+When user enables the IAA device for ``QPL`` compression, it is recommended
+to add ``-mem-prealloc`` parameter to the destination boot parameters. This
+parameter can avoid the occurrence of I/O page fault and reduce the overhead
+of IAA compression and decompression.
+
+The example of booting with ``-mem-prealloc`` parameter
+
+.. code-block:: shell
+
+ $qemu-system-x86_64 --enable-kvm -cpu host --mem-prealloc ...
+
+
+An example about I/O page fault measurement of destination without
+``-mem-prealloc``, the ``svm_prq`` indicates the number of I/O page fault
+occurrences and processing time.
+
+.. code-block:: shell
+
+ #echo 1 > /sys/kernel/debug/iommu/intel/dmar_perf_latency
+ #echo 2 > /sys/kernel/debug/iommu/intel/dmar_perf_latency
+ #echo 3 > /sys/kernel/debug/iommu/intel/dmar_perf_latency
+ #echo 4 > /sys/kernel/debug/iommu/intel/dmar_perf_latency
+ #cat /sys/kernel/debug/iommu/intel/dmar_perf_latency
+ IOMMU: dmar18 Register Base Address: c87fc000
+ <0.1us 0.1us-1us 1us-10us 10us-100us 100us-1ms 1ms-10ms >=10ms min(us) max(us) average(us)
+ inv_iotlb 0 286 123 0 0 0 0 0 1 0
+ inv_devtlb 0 276 133 0 0 0 0 0 2 0
+ inv_iec 0 0 0 0 0 0 0 0 0 0
+ svm_prq 0 0 25206 364 395 0 0 1 556 9
diff --git a/docs/devel/migration/uadk-compression.rst b/docs/devel/migration/uadk-compression.rst
new file mode 100644
index 0000000..3f73345
--- /dev/null
+++ b/docs/devel/migration/uadk-compression.rst
@@ -0,0 +1,144 @@
+=========================================================
+User Space Accelerator Development Kit (UADK) Compression
+=========================================================
+UADK is a general-purpose user space accelerator framework that uses shared
+virtual addressing (SVA) to provide a unified programming interface for
+hardware acceleration of cryptographic and compression algorithms.
+
+UADK includes Unified/User-space-access-intended Accelerator Framework (UACCE),
+which enables hardware accelerators from different vendors that support SVA to
+adapt to UADK.
+
+Currently, HiSilicon Kunpeng hardware accelerators have been registered with
+UACCE. Through the UADK framework, users can run cryptographic and compression
+algorithms using hardware accelerators instead of CPUs, freeing up CPU
+computing power and improving computing performance.
+
+https://github.com/Linaro/uadk/tree/master/docs
+
+UADK Framework
+==============
+UADK consists of UACCE, vendors' drivers, and an algorithm layer. UADK requires
+the hardware accelerator to support SVA, and the operating system to support
+IOMMU and SVA. Hardware accelerators from different vendors are registered as
+different character devices with UACCE by using kernel-mode drivers of the
+vendors. A user can access the hardware accelerators by performing user-mode
+operations on the character devices.
+
+::
+
+ +----------------------------------+
+ | apps |
+ +----+------------------------+----+
+ | |
+ | |
+ +-------+--------+ +-------+-------+
+ | scheduler | | alg libraries |
+ +-------+--------+ +-------+-------+
+ | |
+ | |
+ | |
+ | +--------+------+
+ | | vendor drivers|
+ | +-+-------------+
+ | |
+ | |
+ +--+------------------+--+
+ | libwd |
+ User +----+-------------+-----+
+ --------------------------------------------------
+ Kernel +--+-----+ +------+
+ | uacce | | smmu |
+ +---+----+ +------+
+ |
+ +---+------------------+
+ | vendor kernel driver |
+ +----------------------+
+ --------------------------------------------------
+ +----------------------+
+ | HW Accelerators |
+ +----------------------+
+
+UADK Installation
+-----------------
+Build UADK
+^^^^^^^^^^
+
+.. code-block:: shell
+
+ git clone https://github.com/Linaro/uadk.git
+ cd uadk
+ mkdir build
+ ./autogen.sh
+ ./configure --prefix=$PWD/build
+ make
+ make install
+
+Without --prefix, UADK will be installed to /usr/local/lib by default.
+If get error:"cannot find -lnuma", please install the libnuma-dev
+
+Run pkg-config libwd to ensure env is setup correctly
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+* export PKG_CONFIG_PATH=$PWD/build/lib/pkgconfig
+* pkg-config libwd --cflags --libs
+ -I/usr/local/include -L/usr/local/lib -lwd
+
+* export PKG_CONFIG_PATH is required on demand.
+ Not required if UADK is installed to /usr/local/lib
+
+UADK Host Kernel Requirements
+-----------------------------
+User needs to make sure that ``UACCE`` is already supported in Linux kernel.
+The kernel version should be at least v5.9 with SVA (Shared Virtual
+Addressing) enabled.
+
+Kernel Configuration
+^^^^^^^^^^^^^^^^^^^^
+
+``UACCE`` could be built as module or built-in.
+
+Here's an example to enable UACCE with hardware accelerator in HiSilicon
+Kunpeng platform.
+
+* CONFIG_IOMMU_SVA_LIB=y
+* CONFIG_ARM_SMMU=y
+* CONFIG_ARM_SMMU_V3=y
+* CONFIG_ARM_SMMU_V3_SVA=y
+* CONFIG_PCI_PASID=y
+* CONFIG_UACCE=y
+* CONFIG_CRYPTO_DEV_HISI_QM=y
+* CONFIG_CRYPTO_DEV_HISI_ZIP=y
+
+Make sure all these above kernel configurations are selected.
+
+Accelerator dev node permissions
+--------------------------------
+Harware accelerators(eg: HiSilicon Kunpeng Zip accelerator) gets registered to
+UADK and char devices are created in dev directory. In order to access resources
+on hardware accelerator devices, write permission should be provided to user.
+
+.. code-block:: shell
+
+ $ sudo chmod 777 /dev/hisi_zip-*
+
+How To Use UADK Compression In QEMU Migration
+---------------------------------------------
+* Make sure UADK is installed as above
+* Build ``QEMU`` with ``--enable-uadk`` parameter
+
+ E.g. configure --target-list=aarch64-softmmu --enable-kvm ``--enable-uadk``
+
+* Enable ``UADK`` compression during migration
+
+ Set ``migrate_set_parameter multifd-compression uadk``
+
+Since UADK uses Shared Virtual Addressing(SVA) and device access virtual memory
+directly it is possible that SMMUv3 may enounter page faults while walking the
+IO page tables. This may impact the performance. In order to mitigate this,
+please make sure to specify ``-mem-prealloc`` parameter to the destination VM
+boot parameters.
+
+Though both UADK and ZLIB are based on the deflate compression algorithm, UADK
+is not fully compatible with ZLIB. Hence, please make sure to use ``uadk`` on
+both source and destination during migration.
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index b2dea54..cd9559e 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -1,11 +1,12 @@
-Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``)
-==================================================================
+Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``)
+===================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
Aspeed evaluation boards. They are based on different releases of the
Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
-AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600
-with dual cores ARM Cortex-A7 CPUs (1.2GHz).
+AST2500 with an ARM1176JZS CPU (800MHz), the AST2600
+with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700
+with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz)
The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C,
etc.
@@ -38,6 +39,10 @@
- ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC
- ``qcom-firework-bmc`` Qualcomm Firework BMC
+AST2700 SoC based machines :
+
+- ``ast2700-evb`` Aspeed AST2700 Evaluation board (Cortex-A35)
+
Supported devices
-----------------
@@ -66,6 +71,7 @@
* eMMC Boot Controller (dummy)
* PECI Controller (minimal)
* I3C Controller
+ * Internal Bridge Controller (SLI dummy)
Missing devices
@@ -95,6 +101,10 @@
https://github.com/openbmc/openbmc/releases
+or directly from the ASPEED Forked OpenBMC GitHub release repository :
+
+ https://github.com/AspeedTech-BMC/openbmc/releases
+
To boot a kernel directly from a Linux build tree:
.. code-block:: bash
@@ -164,6 +174,27 @@
-M ast2500-evb,bmc-console=uart3
+
+Boot the AST2700 machine from the flash image, use an MTD drive :
+
+.. code-block:: bash
+
+ IMGDIR=ast2700-default
+ UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
+
+ $ qemu-system-aarch64 -M ast2700-evb \
+ -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
+ -device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
+ -device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
+ -device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
+ -device loader,cpu-num=0,addr=0x430000000 \
+ -device loader,cpu-num=1,addr=0x430000000 \
+ -device loader,cpu-num=2,addr=0x430000000 \
+ -device loader,cpu-num=3,addr=0x430000000 \
+ -smp 4 \
+ -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd \
+ -nographic
+
Aspeed minibmc family boards (``ast1030-evb``)
==================================================================
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 93ca87f..40dc0e4 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -178,6 +178,12 @@
#define AST2600_EVB_HW_STRAP1 0x000000C0
#define AST2600_EVB_HW_STRAP2 0x00000003
+#ifdef TARGET_AARCH64
+/* AST2700 evb hardware value */
+#define AST2700_EVB_HW_STRAP1 0x000000C0
+#define AST2700_EVB_HW_STRAP2 0x00000003
+#endif
+
/* Tacoma hardware value */
#define TACOMA_BMC_HW_STRAP1 0x00000000
#define TACOMA_BMC_HW_STRAP2 0x00000040
@@ -1588,6 +1594,26 @@
aspeed_machine_class_init_cpus_defaults(mc);
}
+#ifdef TARGET_AARCH64
+static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
+ amc->soc_name = "ast2700-a0";
+ amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
+ amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
+ amc->fmc_model = "w25q01jvq";
+ amc->spi_model = "w25q512jv";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
+ amc->uart_default = ASPEED_DEV_UART12;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+#endif
+
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
void *data)
{
@@ -1711,6 +1737,12 @@
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
+#ifdef TARGET_AARCH64
+ }, {
+ .name = MACHINE_TYPE_NAME("ast2700-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_ast2700_evb_class_init,
+#endif
}, {
.name = TYPE_ASPEED_MACHINE,
.parent = TYPE_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
new file mode 100644
index 0000000..b6876b4
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0.c
@@ -0,0 +1,648 @@
+/*
+ * ASPEED SoC 27x0 family
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Implementation extracted from the AST2600 and adapted for AST27x0.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "hw/i2c/aspeed_i2c.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/arm_gicv3.h"
+#include "qapi/qmp/qlist.h"
+#include "qemu/log.h"
+
+static const hwaddr aspeed_soc_ast2700_memmap[] = {
+ [ASPEED_DEV_SPI_BOOT] = 0x400000000,
+ [ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_SDMC] = 0x12C00000,
+ [ASPEED_DEV_SCU] = 0x12C02000,
+ [ASPEED_DEV_SCUIO] = 0x14C02000,
+ [ASPEED_DEV_UART0] = 0X14C33000,
+ [ASPEED_DEV_UART1] = 0X14C33100,
+ [ASPEED_DEV_UART2] = 0X14C33200,
+ [ASPEED_DEV_UART3] = 0X14C33300,
+ [ASPEED_DEV_UART4] = 0X12C1A000,
+ [ASPEED_DEV_UART5] = 0X14C33400,
+ [ASPEED_DEV_UART6] = 0X14C33500,
+ [ASPEED_DEV_UART7] = 0X14C33600,
+ [ASPEED_DEV_UART8] = 0X14C33700,
+ [ASPEED_DEV_UART9] = 0X14C33800,
+ [ASPEED_DEV_UART10] = 0X14C33900,
+ [ASPEED_DEV_UART11] = 0X14C33A00,
+ [ASPEED_DEV_UART12] = 0X14C33B00,
+ [ASPEED_DEV_WDT] = 0x14C37000,
+ [ASPEED_DEV_VUART] = 0X14C30000,
+ [ASPEED_DEV_FMC] = 0x14000000,
+ [ASPEED_DEV_SPI0] = 0x14010000,
+ [ASPEED_DEV_SPI1] = 0x14020000,
+ [ASPEED_DEV_SPI2] = 0x14030000,
+ [ASPEED_DEV_SDRAM] = 0x400000000,
+ [ASPEED_DEV_MII1] = 0x14040000,
+ [ASPEED_DEV_MII2] = 0x14040008,
+ [ASPEED_DEV_MII3] = 0x14040010,
+ [ASPEED_DEV_ETH1] = 0x14050000,
+ [ASPEED_DEV_ETH2] = 0x14060000,
+ [ASPEED_DEV_ETH3] = 0x14070000,
+ [ASPEED_DEV_EMMC] = 0x12090000,
+ [ASPEED_DEV_INTC] = 0x12100000,
+ [ASPEED_DEV_SLI] = 0x12C17000,
+ [ASPEED_DEV_SLIIO] = 0x14C1E000,
+ [ASPEED_GIC_DIST] = 0x12200000,
+ [ASPEED_GIC_REDIST] = 0x12280000,
+};
+
+#define AST2700_MAX_IRQ 288
+
+/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
+static const int aspeed_soc_ast2700_irqmap[] = {
+ [ASPEED_DEV_UART0] = 132,
+ [ASPEED_DEV_UART1] = 132,
+ [ASPEED_DEV_UART2] = 132,
+ [ASPEED_DEV_UART3] = 132,
+ [ASPEED_DEV_UART4] = 8,
+ [ASPEED_DEV_UART5] = 132,
+ [ASPEED_DEV_UART6] = 132,
+ [ASPEED_DEV_UART7] = 132,
+ [ASPEED_DEV_UART8] = 132,
+ [ASPEED_DEV_UART9] = 132,
+ [ASPEED_DEV_UART10] = 132,
+ [ASPEED_DEV_UART11] = 132,
+ [ASPEED_DEV_UART12] = 132,
+ [ASPEED_DEV_FMC] = 131,
+ [ASPEED_DEV_SDMC] = 0,
+ [ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_ADC] = 130,
+ [ASPEED_DEV_XDMA] = 5,
+ [ASPEED_DEV_EMMC] = 15,
+ [ASPEED_DEV_GPIO] = 11,
+ [ASPEED_DEV_GPIO_1_8V] = 130,
+ [ASPEED_DEV_RTC] = 13,
+ [ASPEED_DEV_TIMER1] = 16,
+ [ASPEED_DEV_TIMER2] = 17,
+ [ASPEED_DEV_TIMER3] = 18,
+ [ASPEED_DEV_TIMER4] = 19,
+ [ASPEED_DEV_TIMER5] = 20,
+ [ASPEED_DEV_TIMER6] = 21,
+ [ASPEED_DEV_TIMER7] = 22,
+ [ASPEED_DEV_TIMER8] = 23,
+ [ASPEED_DEV_WDT] = 131,
+ [ASPEED_DEV_PWM] = 131,
+ [ASPEED_DEV_LPC] = 128,
+ [ASPEED_DEV_IBT] = 128,
+ [ASPEED_DEV_I2C] = 130,
+ [ASPEED_DEV_PECI] = 133,
+ [ASPEED_DEV_ETH1] = 132,
+ [ASPEED_DEV_ETH2] = 132,
+ [ASPEED_DEV_ETH3] = 132,
+ [ASPEED_DEV_HACE] = 4,
+ [ASPEED_DEV_KCS] = 128,
+ [ASPEED_DEV_DP] = 28,
+ [ASPEED_DEV_I3C] = 131,
+};
+
+/* GICINT 128 */
+static const int aspeed_soc_ast2700_gic128_intcmap[] = {
+ [ASPEED_DEV_LPC] = 0,
+ [ASPEED_DEV_IBT] = 2,
+ [ASPEED_DEV_KCS] = 4,
+};
+
+/* GICINT 130 */
+static const int aspeed_soc_ast2700_gic130_intcmap[] = {
+ [ASPEED_DEV_I2C] = 0,
+ [ASPEED_DEV_ADC] = 16,
+ [ASPEED_DEV_GPIO_1_8V] = 18,
+};
+
+/* GICINT 131 */
+static const int aspeed_soc_ast2700_gic131_intcmap[] = {
+ [ASPEED_DEV_I3C] = 0,
+ [ASPEED_DEV_WDT] = 16,
+ [ASPEED_DEV_FMC] = 25,
+ [ASPEED_DEV_PWM] = 29,
+};
+
+/* GICINT 132 */
+static const int aspeed_soc_ast2700_gic132_intcmap[] = {
+ [ASPEED_DEV_ETH1] = 0,
+ [ASPEED_DEV_ETH2] = 1,
+ [ASPEED_DEV_ETH3] = 2,
+ [ASPEED_DEV_UART0] = 7,
+ [ASPEED_DEV_UART1] = 8,
+ [ASPEED_DEV_UART2] = 9,
+ [ASPEED_DEV_UART3] = 10,
+ [ASPEED_DEV_UART5] = 11,
+ [ASPEED_DEV_UART6] = 12,
+ [ASPEED_DEV_UART7] = 13,
+ [ASPEED_DEV_UART8] = 14,
+ [ASPEED_DEV_UART9] = 15,
+ [ASPEED_DEV_UART10] = 16,
+ [ASPEED_DEV_UART11] = 17,
+ [ASPEED_DEV_UART12] = 18,
+};
+
+/* GICINT 133 */
+static const int aspeed_soc_ast2700_gic133_intcmap[] = {
+ [ASPEED_DEV_PECI] = 4,
+};
+
+/* GICINT 128 ~ 136 */
+struct gic_intc_irq_info {
+ int irq;
+ const int *ptr;
+};
+
+static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = {
+ {128, aspeed_soc_ast2700_gic128_intcmap},
+ {129, NULL},
+ {130, aspeed_soc_ast2700_gic130_intcmap},
+ {131, aspeed_soc_ast2700_gic131_intcmap},
+ {132, aspeed_soc_ast2700_gic132_intcmap},
+ {133, aspeed_soc_ast2700_gic133_intcmap},
+ {134, NULL},
+ {135, NULL},
+ {136, NULL},
+};
+
+static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
+{
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
+ assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
+ return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
+ aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]);
+ }
+ }
+
+ return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
+}
+
+static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n",
+ __func__, addr);
+ return 0;
+}
+
+static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedSoCState *s = ASPEED_SOC(opaque);
+ ram_addr_t ram_size;
+ MemTxResult result;
+
+ ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+ &error_abort);
+
+ /*
+ * Emulate ddr capacity hardware behavior.
+ * If writes the data to the address which is beyond the ram size,
+ * it would write the data to the "address % ram_size".
+ */
+ result = address_space_write(&s->dram_as, addr % ram_size,
+ MEMTXATTRS_UNSPECIFIED, &data, 4);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: DRAM write failed, addr:0x%" HWADDR_PRIx
+ ", data :0x%" PRIx64 "\n",
+ __func__, addr % ram_size, data);
+ }
+}
+
+static const MemoryRegionOps aspeed_ram_capacity_ops = {
+ .read = aspeed_ram_capacity_read,
+ .write = aspeed_ram_capacity_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
+/*
+ * SDMC should be realized first to get correct RAM size and max size
+ * values
+ */
+static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
+{
+ ram_addr_t ram_size, max_ram_size;
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
+ AspeedSoCState *s = ASPEED_SOC(dev);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+ &error_abort);
+ max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
+ &error_abort);
+
+ memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
+ ram_size);
+ memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
+ address_space_init(&s->dram_as, s->dram_mr, "dram");
+
+ /*
+ * Add a memory region beyond the RAM region to emulate
+ * ddr capacity hardware behavior.
+ */
+ if (ram_size < max_ram_size) {
+ memory_region_init_io(&a->dram_empty, OBJECT(s),
+ &aspeed_ram_capacity_ops, s,
+ "ram-empty", max_ram_size - ram_size);
+
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SDRAM] + ram_size,
+ &a->dram_empty);
+ }
+
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
+ return true;
+}
+
+static void aspeed_soc_ast2700_init(Object *obj)
+{
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i;
+ char socname[8];
+ char typename[64];
+
+ if (sscanf(sc->name, "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
+
+ for (i = 0; i < sc->num_cpus; i++) {
+ object_initialize_child(obj, "cpu[*]", &a->cpu[i],
+ aspeed_soc_cpu_type(sc));
+ }
+
+ object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
+
+ object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
+ sc->silicon_rev);
+ object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
+ "hw-strap1");
+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
+ "hw-strap2");
+ object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
+ "hw-prot-key");
+
+ object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
+ qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
+ sc->silicon_rev);
+
+ snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
+ object_initialize_child(obj, "fmc", &s->fmc, typename);
+
+ for (i = 0; i < sc->spis_num; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname);
+ object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
+ }
+
+ snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
+ object_initialize_child(obj, "sdmc", &s->sdmc, typename);
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
+ "ram-size");
+
+ for (i = 0; i < sc->wdts_num; i++) {
+ snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
+ object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
+ }
+
+ for (i = 0; i < sc->macs_num; i++) {
+ object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
+ TYPE_FTGMAC100);
+
+ object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
+ }
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
+ object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
+ object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
+}
+
+/*
+ * ASPEED ast2700 has 0x0 as cluster ID
+ *
+ * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1
+ */
+static uint64_t aspeed_calc_affinity(int cpu)
+{
+ return (0x0 << ARM_AFF1_SHIFT) | cpu;
+}
+
+static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
+{
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
+ AspeedSoCState *s = ASPEED_SOC(dev);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ SysBusDevice *gicbusdev;
+ DeviceState *gicdev;
+ QList *redist_region_count;
+ int i;
+
+ gicbusdev = SYS_BUS_DEVICE(&a->gic);
+ gicdev = DEVICE(&a->gic);
+ qdev_prop_set_uint32(gicdev, "revision", 3);
+ qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
+ qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ);
+
+ redist_region_count = qlist_new();
+ qlist_append_int(redist_region_count, sc->num_cpus);
+ qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
+
+ if (!sysbus_realize(gicbusdev, errp)) {
+ return false;
+ }
+ sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
+ sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
+
+ for (i = 0; i < sc->num_cpus; i++) {
+ DeviceState *cpudev = DEVICE(&a->cpu[i]);
+ int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7;
+ int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
+
+ const int timer_irq[] = {
+ [GTIMER_PHYS] = 14,
+ [GTIMER_VIRT] = 11,
+ [GTIMER_HYP] = 10,
+ [GTIMER_SEC] = 13,
+ };
+ int j;
+
+ for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
+ qdev_connect_gpio_out(cpudev, j,
+ qdev_get_gpio_in(gicdev, ppibase + timer_irq[j]));
+ }
+
+ qemu_irq irq = qdev_get_gpio_in(gicdev,
+ ppibase + ARCH_GIC_MAINT_IRQ);
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
+ 0, irq);
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
+ qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ));
+
+ sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
+ sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+ sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus,
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
+ sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
+ }
+
+ return true;
+}
+
+static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
+{
+ int i;
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
+ AspeedSoCState *s = ASPEED_SOC(dev);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
+ g_autofree char *sram_name = NULL;
+
+ /* Default boot region (SPI memory or ROMs) */
+ memory_region_init(&s->spi_boot_container, OBJECT(s),
+ "aspeed.spi_boot_container", 0x400000000);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
+ &s->spi_boot_container);
+
+ /* CPU */
+ for (i = 0; i < sc->num_cpus; i++) {
+ object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
+ aspeed_calc_affinity(i), &error_abort);
+
+ object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
+ &error_abort);
+ object_property_set_link(OBJECT(&a->cpu[i]), "memory",
+ OBJECT(s->memory), &error_abort);
+
+ if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
+ return;
+ }
+ }
+
+ /* GIC */
+ if (!aspeed_soc_ast2700_gic_realize(dev, errp)) {
+ return;
+ }
+
+ /* INTC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
+ sc->memmap[ASPEED_DEV_INTC]);
+
+ /* GICINT orgates -> INTC -> GIC */
+ for (i = 0; i < ic->num_ints; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc), i));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
+ qdev_get_gpio_in(DEVICE(&a->gic),
+ aspeed_soc_ast2700_gic_intcmap[i].irq));
+ }
+
+ /* SRAM */
+ sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
+ if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
+ errp)) {
+ return;
+ }
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SRAM], &s->sram);
+
+ /* SCU */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+
+ /* SCU1 */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
+ sc->memmap[ASPEED_DEV_SCUIO]);
+
+ /* UART */
+ if (!aspeed_soc_uart_realize(s, errp)) {
+ return;
+ }
+
+ /* FMC, The number of CS is set at the board level */
+ object_property_set_int(OBJECT(&s->fmc), "dram-base",
+ sc->memmap[ASPEED_DEV_SDRAM],
+ &error_abort);
+ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
+ ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+
+ /* Set up an alias on the FMC CE0 region (boot default) */
+ MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
+ memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
+ fmc0_mmio, 0, memory_region_size(fmc0_mmio));
+ memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
+
+ /* SPI */
+ for (i = 0; i < sc->spis_num; i++) {
+ object_property_set_link(OBJECT(&s->spi[i]), "dram",
+ OBJECT(s->dram_mr), &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
+ sc->memmap[ASPEED_DEV_SPI0 + i]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
+ ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
+ }
+
+ /*
+ * SDMC - SDRAM Memory Controller
+ * The SDMC controller is unlocked at SPL stage.
+ * At present, only supports to emulate booting
+ * start from u-boot stage. Set SDMC controller
+ * unlocked by default. It is a temporarily solution.
+ */
+ object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
+ sc->memmap[ASPEED_DEV_SDMC]);
+
+ /* RAM */
+ if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
+ return;
+ }
+
+ for (i = 0; i < sc->macs_num; i++) {
+ object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
+ sc->memmap[ASPEED_DEV_ETH1 + i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
+
+ object_property_set_link(OBJECT(&s->mii[i]), "nic",
+ OBJECT(&s->ftgmac100[i]), &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
+ sc->memmap[ASPEED_DEV_MII1 + i]);
+ }
+
+ /* Watch dog */
+ for (i = 0; i < sc->wdts_num; i++) {
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
+
+ object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+ }
+
+ /* SLI */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]);
+
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0,
+ sc->memmap[ASPEED_DEV_SLIIO]);
+
+ create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
+ create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
+ create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
+ create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000);
+ create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
+}
+
+static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a35"),
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast2700_realize;
+
+ sc->name = "ast2700-a0";
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST2700_A0_SILICON_REV;
+ sc->sram_size = 0x20000;
+ sc->spis_num = 3;
+ sc->wdts_num = 8;
+ sc->macs_num = 1;
+ sc->uarts_num = 13;
+ sc->num_cpus = 4;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast2700_irqmap;
+ sc->memmap = aspeed_soc_ast2700_memmap;
+ sc->get_irq = aspeed_soc_ast2700_get_irq;
+}
+
+static const TypeInfo aspeed_soc_ast27x0_types[] = {
+ {
+ .name = TYPE_ASPEED27X0_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(Aspeed27x0SoCState),
+ .abstract = true,
+ }, {
+ .name = "ast2700-a0",
+ .parent = TYPE_ASPEED27X0_SOC,
+ .instance_init = aspeed_soc_ast2700_init,
+ .class_init = aspeed_soc_ast2700_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_soc_ast27x0_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index aefde0c..0c07ab5 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -49,6 +49,7 @@
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
+arm_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
diff --git a/hw/arm/xen_arm.c b/hw/arm/xen_arm.c
index 15fa7df..6fad829e 100644
--- a/hw/arm/xen_arm.c
+++ b/hw/arm/xen_arm.c
@@ -125,6 +125,11 @@
GUEST_RAM1_BASE, ram_size[1]);
memory_region_add_subregion(sysmem, GUEST_RAM1_BASE, &ram_hi);
}
+
+ /* Setup support for grants. */
+ memory_region_init_ram(&xen_grants, NULL, "xen.grants", block_len,
+ &error_fatal);
+ memory_region_add_subregion(sysmem, XEN_GRANT_ADDR_OFF, &xen_grants);
}
void arch_handle_ioreq(XenIOState *state, ioreq_t *req)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index d79d6f4..f13350b 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -659,7 +659,7 @@
const PropertyInfo qdev_prop_multifd_compression = {
.name = "MultiFDCompression",
.description = "multifd_compression values, "
- "none/zlib/zstd",
+ "none/zlib/zstd/qpl/uadk",
.enum_table = &MultiFDCompression_lookup,
.get = qdev_propinfo_get_enum,
.set = qdev_propinfo_set_enum,
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
new file mode 100644
index 0000000..7515558
--- /dev/null
+++ b/hw/intc/aspeed_intc.c
@@ -0,0 +1,361 @@
+/*
+ * ASPEED INTC Controller
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/intc/aspeed_intc.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/registerfields.h"
+#include "qapi/error.h"
+
+/* INTC Registers */
+REG32(GICINT128_EN, 0x1000)
+REG32(GICINT128_STATUS, 0x1004)
+REG32(GICINT129_EN, 0x1100)
+REG32(GICINT129_STATUS, 0x1104)
+REG32(GICINT130_EN, 0x1200)
+REG32(GICINT130_STATUS, 0x1204)
+REG32(GICINT131_EN, 0x1300)
+REG32(GICINT131_STATUS, 0x1304)
+REG32(GICINT132_EN, 0x1400)
+REG32(GICINT132_STATUS, 0x1404)
+REG32(GICINT133_EN, 0x1500)
+REG32(GICINT133_STATUS, 0x1504)
+REG32(GICINT134_EN, 0x1600)
+REG32(GICINT134_STATUS, 0x1604)
+REG32(GICINT135_EN, 0x1700)
+REG32(GICINT135_STATUS, 0x1704)
+REG32(GICINT136_EN, 0x1800)
+REG32(GICINT136_STATUS, 0x1804)
+
+#define GICINT_STATUS_BASE R_GICINT128_STATUS
+
+static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
+{
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+
+ if (irq >= aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
+ __func__, irq);
+ return;
+ }
+
+ trace_aspeed_intc_update_irq(irq, level);
+ qemu_set_irq(s->output_pins[irq], level);
+}
+
+/*
+ * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
+ * Utilize "address & 0x0f00" to get the irq and irq output pin index
+ * The value of irq should be 0 to num_ints.
+ * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
+ */
+static void aspeed_intc_set_irq(void *opaque, int irq, int level)
+{
+ AspeedINTCState *s = (AspeedINTCState *)opaque;
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ uint32_t status_addr = GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
+ uint32_t select = 0;
+ uint32_t enable;
+ int i;
+
+ if (irq >= aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
+ __func__, irq);
+ return;
+ }
+
+ trace_aspeed_intc_set_irq(irq, level);
+ enable = s->enable[irq];
+
+ if (!level) {
+ return;
+ }
+
+ for (i = 0; i < aic->num_lines; i++) {
+ if (s->orgates[irq].levels[i]) {
+ if (enable & BIT(i)) {
+ select |= BIT(i);
+ }
+ }
+ }
+
+ if (!select) {
+ return;
+ }
+
+ trace_aspeed_intc_select(select);
+
+ if (s->mask[irq] || s->regs[status_addr]) {
+ /*
+ * a. mask is not 0 means in ISR mode
+ * sources interrupt routine are executing.
+ * b. status register value is not 0 means previous
+ * source interrupt does not be executed, yet.
+ *
+ * save source interrupt to pending variable.
+ */
+ s->pending[irq] |= select;
+ trace_aspeed_intc_pending_irq(irq, s->pending[irq]);
+ } else {
+ /*
+ * notify firmware which source interrupt are coming
+ * by setting status register
+ */
+ s->regs[status_addr] = select;
+ trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]);
+ aspeed_intc_update(s, irq, 1);
+ }
+}
+
+static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ uint32_t addr = offset >> 2;
+ uint32_t value = 0;
+
+ if (addr >= ASPEED_INTC_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return 0;
+ }
+
+ value = s->regs[addr];
+ trace_aspeed_intc_read(offset, size, value);
+
+ return value;
+}
+
+static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ uint32_t addr = offset >> 2;
+ uint32_t old_enable;
+ uint32_t change;
+ uint32_t irq;
+
+ if (addr >= ASPEED_INTC_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ trace_aspeed_intc_write(offset, size, data);
+
+ switch (addr) {
+ case R_GICINT128_EN:
+ case R_GICINT129_EN:
+ case R_GICINT130_EN:
+ case R_GICINT131_EN:
+ case R_GICINT132_EN:
+ case R_GICINT133_EN:
+ case R_GICINT134_EN:
+ case R_GICINT135_EN:
+ case R_GICINT136_EN:
+ irq = (offset & 0x0f00) >> 8;
+
+ if (irq >= aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
+ __func__, irq);
+ return;
+ }
+
+ /*
+ * These registers are used for enable sources interrupt and
+ * mask and unmask source interrupt while executing source ISR.
+ */
+
+ /* disable all source interrupt */
+ if (!data && !s->enable[irq]) {
+ s->regs[addr] = data;
+ return;
+ }
+
+ old_enable = s->enable[irq];
+ s->enable[irq] |= data;
+
+ /* enable new source interrupt */
+ if (old_enable != s->enable[irq]) {
+ trace_aspeed_intc_enable(s->enable[irq]);
+ s->regs[addr] = data;
+ return;
+ }
+
+ /* mask and unmask source interrupt */
+ change = s->regs[addr] ^ data;
+ if (change & data) {
+ s->mask[irq] &= ~change;
+ trace_aspeed_intc_unmask(change, s->mask[irq]);
+ } else {
+ s->mask[irq] |= change;
+ trace_aspeed_intc_mask(change, s->mask[irq]);
+ }
+ s->regs[addr] = data;
+ break;
+ case R_GICINT128_STATUS:
+ case R_GICINT129_STATUS:
+ case R_GICINT130_STATUS:
+ case R_GICINT131_STATUS:
+ case R_GICINT132_STATUS:
+ case R_GICINT133_STATUS:
+ case R_GICINT134_STATUS:
+ case R_GICINT135_STATUS:
+ case R_GICINT136_STATUS:
+ irq = (offset & 0x0f00) >> 8;
+
+ if (irq >= aic->num_ints) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
+ __func__, irq);
+ return;
+ }
+
+ /* clear status */
+ s->regs[addr] &= ~data;
+
+ /*
+ * These status registers are used for notify sources ISR are executed.
+ * If one source ISR is executed, it will clear one bit.
+ * If it clear all bits, it means to initialize this register status
+ * rather than sources ISR are executed.
+ */
+ if (data == 0xffffffff) {
+ return;
+ }
+
+ /* All source ISR execution are done */
+ if (!s->regs[addr]) {
+ trace_aspeed_intc_all_isr_done(irq);
+ if (s->pending[irq]) {
+ /*
+ * handle pending source interrupt
+ * notify firmware which source interrupt are pending
+ * by setting status register
+ */
+ s->regs[addr] = s->pending[irq];
+ s->pending[irq] = 0;
+ trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
+ aspeed_intc_update(s, irq, 1);
+ } else {
+ /* clear irq */
+ trace_aspeed_intc_clear_irq(irq, 0);
+ aspeed_intc_update(s, irq, 0);
+ }
+ }
+ break;
+ default:
+ s->regs[addr] = data;
+ break;
+ }
+
+ return;
+}
+
+static const MemoryRegionOps aspeed_intc_ops = {
+ .read = aspeed_intc_read,
+ .write = aspeed_intc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static void aspeed_intc_instance_init(Object *obj)
+{
+ AspeedINTCState *s = ASPEED_INTC(obj);
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ int i;
+
+ assert(aic->num_ints <= ASPEED_INTC_NR_INTS);
+ for (i = 0; i < aic->num_ints; i++) {
+ object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i],
+ TYPE_OR_IRQ);
+ object_property_set_int(OBJECT(&s->orgates[i]), "num-lines",
+ aic->num_lines, &error_abort);
+ }
+}
+
+static void aspeed_intc_reset(DeviceState *dev)
+{
+ AspeedINTCState *s = ASPEED_INTC(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+ memset(s->enable, 0, sizeof(s->enable));
+ memset(s->mask, 0, sizeof(s->mask));
+ memset(s->pending, 0, sizeof(s->pending));
+}
+
+static void aspeed_intc_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ AspeedINTCState *s = ASPEED_INTC(dev);
+ AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
+ int i;
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
+ TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS << 2);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+ qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints);
+
+ for (i = 0; i < aic->num_ints; i++) {
+ if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
+ return;
+ }
+ sysbus_init_irq(sbd, &s->output_pins[i]);
+ }
+}
+
+static void aspeed_intc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "ASPEED INTC Controller";
+ dc->realize = aspeed_intc_realize;
+ dc->reset = aspeed_intc_reset;
+ dc->vmsd = NULL;
+}
+
+static const TypeInfo aspeed_intc_info = {
+ .name = TYPE_ASPEED_INTC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = aspeed_intc_instance_init,
+ .instance_size = sizeof(AspeedINTCState),
+ .class_init = aspeed_intc_class_init,
+ .class_size = sizeof(AspeedINTCClass),
+ .abstract = true,
+};
+
+static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 INTC Controller";
+ aic->num_lines = 32;
+ aic->num_ints = 9;
+}
+
+static const TypeInfo aspeed_2700_intc_info = {
+ .name = TYPE_ASPEED_2700_INTC,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700_intc_class_init,
+};
+
+static void aspeed_intc_register_types(void)
+{
+ type_register_static(&aspeed_intc_info);
+ type_register_static(&aspeed_2700_intc_info);
+}
+
+type_init(aspeed_intc_register_types);
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 0d1b7d0..afd1aa5 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -14,6 +14,7 @@
))
system_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
+system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_intc.c'))
system_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
system_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index b815cea..3dcf147 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -79,6 +79,19 @@
aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+# aspeed_intc.c
+aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_intc_set_irq(int irq, int level) "Set IRQ %d: %d"
+aspeed_intc_clear_irq(int irq, int level) "Clear IRQ %d: %d"
+aspeed_intc_update_irq(int irq, int level) "Update IRQ: %d: %d"
+aspeed_intc_pending_irq(int irq, uint32_t value) "Pending IRQ: %d: 0x%x"
+aspeed_intc_trigger_irq(int irq, uint32_t value) "Trigger IRQ: %d: 0x%x"
+aspeed_intc_all_isr_done(int irq) "All source ISR execution are done: %d"
+aspeed_intc_enable(uint32_t value) "Enable: 0x%x"
+aspeed_intc_select(uint32_t value) "Select: 0x%x"
+aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x"
+aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x"
# arm_gic.c
gic_enable_irq(int irq) "irq %d enabled"
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 1ac04b6..451e837 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -134,6 +134,48 @@
#define AST2600_CLK TO_REG(0x40)
+#define AST2700_SILICON_REV TO_REG(0x00)
+#define AST2700_HW_STRAP1 TO_REG(0x10)
+#define AST2700_HW_STRAP1_CLR TO_REG(0x14)
+#define AST2700_HW_STRAP1_LOCK TO_REG(0x20)
+#define AST2700_HW_STRAP1_SEC1 TO_REG(0x24)
+#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
+#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
+
+#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
+#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
+#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)
+#define AST2700_SCU_DPLL_PARAM TO_REG(0x308)
+#define AST2700_SCU_DPLL_EXT_PARAM TO_REG(0x30c)
+#define AST2700_SCU_MPLL_PARAM TO_REG(0x310)
+#define AST2700_SCU_MPLL_EXT_PARAM TO_REG(0x314)
+#define AST2700_SCU_D1CLK_PARAM TO_REG(0x320)
+#define AST2700_SCU_D2CLK_PARAM TO_REG(0x330)
+#define AST2700_SCU_CRT1CLK_PARAM TO_REG(0x340)
+#define AST2700_SCU_CRT2CLK_PARAM TO_REG(0x350)
+#define AST2700_SCU_MPHYCLK_PARAM TO_REG(0x360)
+#define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0)
+#define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780)
+#define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784)
+
+#define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240)
+#define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244)
+#define AST2700_SCUIO_CLK_STOP_CTL_2 TO_REG(0x260)
+#define AST2700_SCUIO_CLK_STOP_CLR_2 TO_REG(0x264)
+#define AST2700_SCUIO_CLK_SEL_1 TO_REG(0x280)
+#define AST2700_SCUIO_CLK_SEL_2 TO_REG(0x284)
+#define AST2700_SCUIO_HPLL_PARAM TO_REG(0x300)
+#define AST2700_SCUIO_HPLL_EXT_PARAM TO_REG(0x304)
+#define AST2700_SCUIO_APLL_PARAM TO_REG(0x310)
+#define AST2700_SCUIO_APLL_EXT_PARAM TO_REG(0x314)
+#define AST2700_SCUIO_DPLL_PARAM TO_REG(0x320)
+#define AST2700_SCUIO_DPLL_EXT_PARAM TO_REG(0x324)
+#define AST2700_SCUIO_DPLL_PARAM_READ TO_REG(0x328)
+#define AST2700_SCUIO_DPLL_EXT_PARAM_READ TO_REG(0x32c)
+#define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330)
+#define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334)
+#define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388)
+
#define SCU_IO_REGION_SIZE 0x1000
static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
@@ -244,6 +286,25 @@
/ asc->apb_divider;
}
+static uint32_t aspeed_2700_scu_get_apb_freq(AspeedSCUState *s)
+{
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
+ uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCU_HPLL_PARAM]);
+
+ return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2700_SCU_CLK_SEL_1]) + 1)
+ / asc->apb_divider;
+}
+
+static uint32_t aspeed_2700_scuio_get_apb_freq(AspeedSCUState *s)
+{
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
+ uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCUIO_HPLL_PARAM]);
+
+ return hpll /
+ (SCUIO_AST2700_CLK_GET_PCLK_DIV(s->regs[AST2700_SCUIO_CLK_SEL_1]) + 1)
+ / asc->apb_divider;
+}
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -258,7 +319,8 @@
switch (reg) {
case RNG_DATA:
- /* On hardware, RNG_DATA works regardless of
+ /*
+ * On hardware, RNG_DATA works regardless of
* the state of the enable bit in RNG_CTRL
*/
s->regs[RNG_DATA] = aspeed_scu_get_random();
@@ -494,6 +556,9 @@
AST2600_A3_SILICON_REV,
AST1030_A0_SILICON_REV,
AST1030_A1_SILICON_REV,
+ AST2700_A0_SILICON_REV,
+ AST2720_A0_SILICON_REV,
+ AST2750_A0_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
@@ -783,6 +848,243 @@
.class_init = aspeed_2600_scu_class_init,
};
+static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AspeedSCUState *s = ASPEED_SCU(opaque);
+ int reg = TO_REG(offset);
+
+ if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return 0;
+ }
+
+ switch (reg) {
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ }
+
+ trace_aspeed_ast2700_scu_read(offset, size, s->regs[reg]);
+ return s->regs[reg];
+}
+
+static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
+ uint64_t data64, unsigned size)
+{
+ AspeedSCUState *s = ASPEED_SCU(opaque);
+ int reg = TO_REG(offset);
+ /* Truncate here so bitwise operations below behave as expected */
+ uint32_t data = data64;
+
+ if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ trace_aspeed_ast2700_scu_write(offset, size, data);
+
+ switch (reg) {
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ break;
+ }
+
+ s->regs[reg] = data;
+}
+
+static const MemoryRegionOps aspeed_ast2700_scu_ops = {
+ .read = aspeed_ast2700_scu_read,
+ .write = aspeed_ast2700_scu_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+ .valid.unaligned = false,
+};
+
+static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
+ [AST2700_SILICON_REV] = AST2700_A0_SILICON_REV,
+ [AST2700_HW_STRAP1] = 0x00000800,
+ [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,
+ [AST2700_HW_STRAP1_LOCK] = 0x00000FFF,
+ [AST2700_HW_STRAP1_SEC1] = 0x000000FF,
+ [AST2700_HW_STRAP1_SEC2] = 0x00000000,
+ [AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCU_HPLL_PARAM] = 0x0000009f,
+ [AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
+ [AST2700_SCU_DPLL_PARAM] = 0x0080009f,
+ [AST2700_SCU_DPLL_EXT_PARAM] = 0x8000004f,
+ [AST2700_SCU_MPLL_PARAM] = 0x00000040,
+ [AST2700_SCU_MPLL_EXT_PARAM] = 0x80000000,
+ [AST2700_SCU_D1CLK_PARAM] = 0x00050002,
+ [AST2700_SCU_D2CLK_PARAM] = 0x00050002,
+ [AST2700_SCU_CRT1CLK_PARAM] = 0x00050002,
+ [AST2700_SCU_CRT2CLK_PARAM] = 0x00050002,
+ [AST2700_SCU_MPHYCLK_PARAM] = 0x0000004c,
+ [AST2700_SCU_FREQ_CNTR] = 0x000375eb,
+ [AST2700_SCU_CPU_SCRATCH_0] = 0x00000000,
+ [AST2700_SCU_CPU_SCRATCH_1] = 0x00000004,
+};
+
+static void aspeed_ast2700_scu_reset(DeviceState *dev)
+{
+ AspeedSCUState *s = ASPEED_SCU(dev);
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+
+ memcpy(s->regs, asc->resets, asc->nr_regs * 4);
+}
+
+static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 System Control Unit";
+ dc->reset = aspeed_ast2700_scu_reset;
+ asc->resets = ast2700_a0_resets;
+ asc->calc_hpll = aspeed_2600_scu_calc_hpll;
+ asc->get_apb = aspeed_2700_scu_get_apb_freq;
+ asc->apb_divider = 4;
+ asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS;
+ asc->clkin_25Mhz = true;
+ asc->ops = &aspeed_ast2700_scu_ops;
+}
+
+static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AspeedSCUState *s = ASPEED_SCU(opaque);
+ int reg = TO_REG(offset);
+ if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return 0;
+ }
+
+ switch (reg) {
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ }
+
+ trace_aspeed_ast2700_scuio_read(offset, size, s->regs[reg]);
+ return s->regs[reg];
+}
+
+static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset,
+ uint64_t data64, unsigned size)
+{
+ AspeedSCUState *s = ASPEED_SCU(opaque);
+ int reg = TO_REG(offset);
+ /* Truncate here so bitwise operations below behave as expected */
+ uint32_t data = data64;
+ bool updated = false;
+
+ if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ trace_aspeed_ast2700_scuio_write(offset, size, data);
+
+ switch (reg) {
+ case AST2700_SCUIO_CLK_STOP_CTL_1:
+ case AST2700_SCUIO_CLK_STOP_CTL_2:
+ s->regs[reg] |= data;
+ updated = true;
+ break;
+ case AST2700_SCUIO_CLK_STOP_CLR_1:
+ case AST2700_SCUIO_CLK_STOP_CLR_2:
+ s->regs[reg - 1] ^= data;
+ updated = true;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ break;
+ }
+
+ if (!updated) {
+ s->regs[reg] = data;
+ }
+}
+
+static const MemoryRegionOps aspeed_ast2700_scuio_ops = {
+ .read = aspeed_ast2700_scuio_read,
+ .write = aspeed_ast2700_scuio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+ .valid.unaligned = false,
+};
+
+static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {
+ [AST2700_SILICON_REV] = 0x06000003,
+ [AST2700_HW_STRAP1] = 0x00000504,
+ [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,
+ [AST2700_HW_STRAP1_LOCK] = 0x00000FFF,
+ [AST2700_HW_STRAP1_SEC1] = 0x000000FF,
+ [AST2700_HW_STRAP1_SEC2] = 0x00000000,
+ [AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCUIO_CLK_STOP_CTL_1] = 0xffff8400,
+ [AST2700_SCUIO_CLK_STOP_CTL_2] = 0x00005f30,
+ [AST2700_SCUIO_CLK_SEL_1] = 0x86900000,
+ [AST2700_SCUIO_CLK_SEL_2] = 0x00400000,
+ [AST2700_SCUIO_HPLL_PARAM] = 0x10000027,
+ [AST2700_SCUIO_HPLL_EXT_PARAM] = 0x80000014,
+ [AST2700_SCUIO_APLL_PARAM] = 0x1000001f,
+ [AST2700_SCUIO_APLL_EXT_PARAM] = 0x8000000f,
+ [AST2700_SCUIO_DPLL_PARAM] = 0x106e42ce,
+ [AST2700_SCUIO_DPLL_EXT_PARAM] = 0x80000167,
+ [AST2700_SCUIO_DPLL_PARAM_READ] = 0x106e42ce,
+ [AST2700_SCUIO_DPLL_EXT_PARAM_READ] = 0x80000167,
+ [AST2700_SCUIO_UARTCLK_GEN] = 0x00014506,
+ [AST2700_SCUIO_HUARTCLK_GEN] = 0x000145c0,
+ [AST2700_SCUIO_CLK_DUTY_MEAS_RST] = 0x0c9100d2,
+};
+
+static void aspeed_2700_scuio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 System Control Unit I/O";
+ dc->reset = aspeed_ast2700_scu_reset;
+ asc->resets = ast2700_a0_resets_io;
+ asc->calc_hpll = aspeed_2600_scu_calc_hpll;
+ asc->get_apb = aspeed_2700_scuio_get_apb_freq;
+ asc->apb_divider = 2;
+ asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS;
+ asc->clkin_25Mhz = true;
+ asc->ops = &aspeed_ast2700_scuio_ops;
+}
+
+static const TypeInfo aspeed_2700_scu_info = {
+ .name = TYPE_ASPEED_2700_SCU,
+ .parent = TYPE_ASPEED_SCU,
+ .instance_size = sizeof(AspeedSCUState),
+ .class_init = aspeed_2700_scu_class_init,
+};
+
+static const TypeInfo aspeed_2700_scuio_info = {
+ .name = TYPE_ASPEED_2700_SCUIO,
+ .parent = TYPE_ASPEED_SCU,
+ .instance_size = sizeof(AspeedSCUState),
+ .class_init = aspeed_2700_scuio_class_init,
+};
+
static const uint32_t ast1030_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
[AST2600_SYS_RST_CTRL] = 0xFFC3FED8,
[AST2600_SYS_RST_CTRL2] = 0x09FFFFFC,
@@ -841,6 +1143,8 @@
type_register_static(&aspeed_2500_scu_info);
type_register_static(&aspeed_2600_scu_info);
type_register_static(&aspeed_1030_scu_info);
+ type_register_static(&aspeed_2700_scu_info);
+ type_register_static(&aspeed_2700_scuio_info);
}
type_init(aspeed_scu_register_types);
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 64cd1a8..93e2e29 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -27,6 +27,7 @@
#define PROT_SOFTLOCKED 0x00
#define PROT_KEY_UNLOCK 0xFC600309
+#define PROT_2700_KEY_UNLOCK 0x1688A8A8
#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
/* Configuration Register */
@@ -54,6 +55,46 @@
#define R_DRAM_TIME (0x8c / 4)
#define R_ECC_ERR_INJECT (0xb4 / 4)
+/* AST2700 Register */
+#define R_2700_PROT (0x00 / 4)
+#define R_INT_STATUS (0x04 / 4)
+#define R_INT_CLEAR (0x08 / 4)
+#define R_INT_MASK (0x0c / 4)
+#define R_MAIN_CONF (0x10 / 4)
+#define R_MAIN_CONTROL (0x14 / 4)
+#define R_MAIN_STATUS (0x18 / 4)
+#define R_ERR_STATUS (0x1c / 4)
+#define R_ECC_FAIL_STATUS (0x78 / 4)
+#define R_ECC_FAIL_ADDR (0x7c / 4)
+#define R_ECC_TESTING_CONTROL (0x80 / 4)
+#define R_PROT_REGION_LOCK_STATUS (0x94 / 4)
+#define R_TEST_FAIL_ADDR (0xd4 / 4)
+#define R_TEST_FAIL_D0 (0xd8 / 4)
+#define R_TEST_FAIL_D1 (0xdc / 4)
+#define R_TEST_FAIL_D2 (0xe0 / 4)
+#define R_TEST_FAIL_D3 (0xe4 / 4)
+#define R_DBG_STATUS (0xf4 / 4)
+#define R_PHY_INTERFACE_STATUS (0xf8 / 4)
+#define R_GRAPHIC_MEM_BASE_ADDR (0x10c / 4)
+#define R_PORT0_INTERFACE_MONITOR0 (0x240 / 4)
+#define R_PORT0_INTERFACE_MONITOR1 (0x244 / 4)
+#define R_PORT0_INTERFACE_MONITOR2 (0x248 / 4)
+#define R_PORT1_INTERFACE_MONITOR0 (0x2c0 / 4)
+#define R_PORT1_INTERFACE_MONITOR1 (0x2c4 / 4)
+#define R_PORT1_INTERFACE_MONITOR2 (0x2c8 / 4)
+#define R_PORT2_INTERFACE_MONITOR0 (0x340 / 4)
+#define R_PORT2_INTERFACE_MONITOR1 (0x344 / 4)
+#define R_PORT2_INTERFACE_MONITOR2 (0x348 / 4)
+#define R_PORT3_INTERFACE_MONITOR0 (0x3c0 / 4)
+#define R_PORT3_INTERFACE_MONITOR1 (0x3c4 / 4)
+#define R_PORT3_INTERFACE_MONITOR2 (0x3c8 / 4)
+#define R_PORT4_INTERFACE_MONITOR0 (0x440 / 4)
+#define R_PORT4_INTERFACE_MONITOR1 (0x444 / 4)
+#define R_PORT4_INTERFACE_MONITOR2 (0x448 / 4)
+#define R_PORT5_INTERFACE_MONITOR0 (0x4c0 / 4)
+#define R_PORT5_INTERFACE_MONITOR1 (0x4c4 / 4)
+#define R_PORT5_INTERFACE_MONITOR2 (0x4c8 / 4)
+
/*
* Configuration register Ox4 (for Aspeed AST2400 SOC)
*
@@ -76,10 +117,6 @@
#define ASPEED_SDMC_VGA_32MB 0x2
#define ASPEED_SDMC_VGA_64MB 0x3
#define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
-#define ASPEED_SDMC_DRAM_64MB 0x0
-#define ASPEED_SDMC_DRAM_128MB 0x1
-#define ASPEED_SDMC_DRAM_256MB 0x2
-#define ASPEED_SDMC_DRAM_512MB 0x3
#define ASPEED_SDMC_READONLY_MASK \
(ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
@@ -100,22 +137,24 @@
#define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
#define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
-/* DRAM size definitions differs */
-#define ASPEED_SDMC_AST2500_128MB 0x0
-#define ASPEED_SDMC_AST2500_256MB 0x1
-#define ASPEED_SDMC_AST2500_512MB 0x2
-#define ASPEED_SDMC_AST2500_1024MB 0x3
-
-#define ASPEED_SDMC_AST2600_256MB 0x0
-#define ASPEED_SDMC_AST2600_512MB 0x1
-#define ASPEED_SDMC_AST2600_1024MB 0x2
-#define ASPEED_SDMC_AST2600_2048MB 0x3
-
#define ASPEED_SDMC_AST2500_READONLY_MASK \
(ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
+/*
+ * Main Configuration register Ox10 (for Aspeed AST2700 SOC and higher)
+ *
+ */
+#define ASPEED_SDMC_AST2700_RESERVED 0xFFFF2082 /* 31:16, 13, 7, 1 */
+#define ASPEED_SDMC_AST2700_DATA_SCRAMBLE (1 << 8)
+#define ASPEED_SDMC_AST2700_ECC_ENABLE (1 << 6)
+#define ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE (1 << 5)
+#define ASPEED_SDMC_AST2700_DRAM_SIZE(x) ((x & 0x7) << 2)
+
+#define ASPEED_SDMC_AST2700_READONLY_MASK \
+ (ASPEED_SDMC_AST2700_RESERVED)
+
static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
{
AspeedSDMCState *s = ASPEED_SDMC(opaque);
@@ -231,7 +270,7 @@
AspeedSDMCState *s = ASPEED_SDMC(dev);
AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
- assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */
+ assert(asc->max_ram_size < 4 * GiB || asc->is_bus64bit);
s->max_ram_size = asc->max_ram_size;
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
@@ -241,8 +280,8 @@
static const VMStateDescription vmstate_aspeed_sdmc = {
.name = "aspeed.sdmc",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
VMSTATE_END_OF_LIST()
@@ -251,6 +290,7 @@
static Property aspeed_sdmc_properties[] = {
DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
+ DEFINE_PROP_BOOL("unlocked", AspeedSDMCState, unlocked, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -311,7 +351,8 @@
uint32_t data)
{
if (reg == R_PROT) {
- s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
+ s->regs[reg] =
+ (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
return;
}
@@ -369,7 +410,8 @@
uint32_t data)
{
if (reg == R_PROT) {
- s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
+ s->regs[reg] =
+ (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
return;
}
@@ -449,8 +491,9 @@
}
if (s->regs[R_PROT] == PROT_HARDLOCKED) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
- __func__);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SDMC is locked until system reset!\n",
+ __func__);
return;
}
@@ -512,12 +555,145 @@
.class_init = aspeed_2600_sdmc_class_init,
};
+static void aspeed_2700_sdmc_reset(DeviceState *dev)
+{
+ AspeedSDMCState *s = ASPEED_SDMC(dev);
+ AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ /* Set ram size bit and defaults values */
+ s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0);
+
+ if (s->unlocked) {
+ s->regs[R_2700_PROT] = PROT_UNLOCKED;
+ }
+}
+
+static uint32_t aspeed_2700_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
+{
+ uint32_t fixed_conf = ASPEED_SDMC_AST2700_PAGE_MATCHING_ENABLE |
+ ASPEED_SDMC_AST2700_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));
+
+ /* Make sure readonly bits are kept */
+ data &= ~ASPEED_SDMC_AST2700_READONLY_MASK;
+
+ return data | fixed_conf;
+}
+
+static void aspeed_2700_sdmc_write(AspeedSDMCState *s, uint32_t reg,
+ uint32_t data)
+{
+ /* Unprotected registers */
+ switch (reg) {
+ case R_INT_STATUS:
+ case R_INT_CLEAR:
+ case R_INT_MASK:
+ case R_MAIN_STATUS:
+ case R_ERR_STATUS:
+ case R_ECC_FAIL_STATUS:
+ case R_ECC_FAIL_ADDR:
+ case R_PROT_REGION_LOCK_STATUS:
+ case R_TEST_FAIL_ADDR:
+ case R_TEST_FAIL_D0:
+ case R_TEST_FAIL_D1:
+ case R_TEST_FAIL_D2:
+ case R_TEST_FAIL_D3:
+ case R_DBG_STATUS:
+ case R_PHY_INTERFACE_STATUS:
+ case R_GRAPHIC_MEM_BASE_ADDR:
+ case R_PORT0_INTERFACE_MONITOR0:
+ case R_PORT0_INTERFACE_MONITOR1:
+ case R_PORT0_INTERFACE_MONITOR2:
+ case R_PORT1_INTERFACE_MONITOR0:
+ case R_PORT1_INTERFACE_MONITOR1:
+ case R_PORT1_INTERFACE_MONITOR2:
+ case R_PORT2_INTERFACE_MONITOR0:
+ case R_PORT2_INTERFACE_MONITOR1:
+ case R_PORT2_INTERFACE_MONITOR2:
+ case R_PORT3_INTERFACE_MONITOR0:
+ case R_PORT3_INTERFACE_MONITOR1:
+ case R_PORT3_INTERFACE_MONITOR2:
+ case R_PORT4_INTERFACE_MONITOR0:
+ case R_PORT4_INTERFACE_MONITOR1:
+ case R_PORT4_INTERFACE_MONITOR2:
+ case R_PORT5_INTERFACE_MONITOR0:
+ case R_PORT5_INTERFACE_MONITOR1:
+ case R_PORT5_INTERFACE_MONITOR2:
+ s->regs[reg] = data;
+ return;
+ }
+
+ if (s->regs[R_2700_PROT] == PROT_HARDLOCKED) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SDMC is locked until system reset!\n",
+ __func__);
+ return;
+ }
+
+ if (reg != R_2700_PROT && s->regs[R_2700_PROT] == PROT_SOFTLOCKED) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SDMC is locked! (write to MCR%02x blocked)\n",
+ __func__, reg * 4);
+ return;
+ }
+
+ switch (reg) {
+ case R_2700_PROT:
+ if (data == PROT_2700_KEY_UNLOCK) {
+ data = PROT_UNLOCKED;
+ } else if (data == PROT_KEY_HARDLOCK) {
+ data = PROT_HARDLOCKED;
+ } else {
+ data = PROT_SOFTLOCKED;
+ }
+ break;
+ case R_MAIN_CONF:
+ data = aspeed_2700_sdmc_compute_conf(s, data);
+ break;
+ case R_MAIN_STATUS:
+ /* Will never return 'busy'. */
+ data &= ~PHY_BUSY_STATE;
+ break;
+ default:
+ break;
+ }
+
+ s->regs[reg] = data;
+}
+
+static const uint64_t
+ aspeed_2700_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB,
+ 2048 * MiB, 4096 * MiB, 8192 * MiB, 0};
+
+static void aspeed_2700_sdmc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 SDRAM Memory Controller";
+ dc->reset = aspeed_2700_sdmc_reset;
+
+ asc->is_bus64bit = true;
+ asc->max_ram_size = 8 * GiB;
+ asc->compute_conf = aspeed_2700_sdmc_compute_conf;
+ asc->write = aspeed_2700_sdmc_write;
+ asc->valid_ram_sizes = aspeed_2700_ram_sizes;
+}
+
+static const TypeInfo aspeed_2700_sdmc_info = {
+ .name = TYPE_ASPEED_2700_SDMC,
+ .parent = TYPE_ASPEED_SDMC,
+ .class_init = aspeed_2700_sdmc_class_init,
+};
+
static void aspeed_sdmc_register_types(void)
{
type_register_static(&aspeed_sdmc_info);
type_register_static(&aspeed_2400_sdmc_info);
type_register_static(&aspeed_2500_sdmc_info);
type_register_static(&aspeed_2600_sdmc_info);
+ type_register_static(&aspeed_2700_sdmc_info);
}
type_init(aspeed_sdmc_register_types);
diff --git a/hw/misc/aspeed_sli.c b/hw/misc/aspeed_sli.c
new file mode 100644
index 0000000..fe720ea
--- /dev/null
+++ b/hw/misc/aspeed_sli.c
@@ -0,0 +1,177 @@
+/*
+ * ASPEED SLI Controller
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/aspeed_sli.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+#define SLI_REGION_SIZE 0x500
+#define TO_REG(addr) ((addr) >> 2)
+
+static uint64_t aspeed_sli_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+ }
+
+ trace_aspeed_sli_read(addr, size, s->regs[reg]);
+ return s->regs[reg];
+}
+
+static void aspeed_sli_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return;
+ }
+
+ trace_aspeed_sli_write(addr, size, data);
+ s->regs[reg] = data;
+}
+
+static uint64_t aspeed_sliio_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return 0;
+ }
+
+ trace_aspeed_sliio_read(addr, size, s->regs[reg]);
+ return s->regs[reg];
+}
+
+static void aspeed_sliio_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedSLIState *s = ASPEED_SLI(opaque);
+ int reg = TO_REG(addr);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr);
+ return;
+ }
+
+ trace_aspeed_sliio_write(addr, size, data);
+ s->regs[reg] = data;
+}
+
+static const MemoryRegionOps aspeed_sli_ops = {
+ .read = aspeed_sli_read,
+ .write = aspeed_sli_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static const MemoryRegionOps aspeed_sliio_ops = {
+ .read = aspeed_sliio_read,
+ .write = aspeed_sliio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_sli_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSLIState *s = ASPEED_SLI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sli_ops, s,
+ TYPE_ASPEED_SLI, SLI_REGION_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_sliio_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSLIState *s = ASPEED_SLI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sliio_ops, s,
+ TYPE_ASPEED_SLI, SLI_REGION_SIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_sli_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Aspeed SLI Controller";
+ dc->realize = aspeed_sli_realize;
+}
+
+static const TypeInfo aspeed_sli_info = {
+ .name = TYPE_ASPEED_SLI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedSLIState),
+ .class_init = aspeed_sli_class_init,
+ .abstract = true,
+};
+
+static void aspeed_2700_sli_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "AST2700 SLI Controller";
+}
+
+static void aspeed_2700_sliio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "AST2700 I/O SLI Controller";
+ dc->realize = aspeed_sliio_realize;
+}
+
+static const TypeInfo aspeed_2700_sli_info = {
+ .name = TYPE_ASPEED_2700_SLI,
+ .parent = TYPE_ASPEED_SLI,
+ .class_init = aspeed_2700_sli_class_init,
+};
+
+static const TypeInfo aspeed_2700_sliio_info = {
+ .name = TYPE_ASPEED_2700_SLIIO,
+ .parent = TYPE_ASPEED_SLI,
+ .class_init = aspeed_2700_sliio_class_init,
+};
+
+static void aspeed_sli_register_types(void)
+{
+ type_register_static(&aspeed_sli_info);
+ type_register_static(&aspeed_2700_sli_info);
+ type_register_static(&aspeed_2700_sliio_info);
+}
+
+type_init(aspeed_sli_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 86596a3..2ca8717 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -136,7 +136,8 @@
'aspeed_sbc.c',
'aspeed_sdmc.c',
'aspeed_xdma.c',
- 'aspeed_peci.c'))
+ 'aspeed_peci.c',
+ 'aspeed_sli.c'))
system_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c'))
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 5d241cb..1be0717 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -93,6 +93,10 @@
# aspeed_scu.c
aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_ast2700_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
# mps2-scc.c
mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
@@ -351,3 +355,10 @@
# iosb.c
iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
+
+# aspeed_sli.c
+aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+
diff --git a/hw/sh4/trace-events b/hw/sh4/trace-events
index 4b61cd5..6bfd7ee 100644
--- a/hw/sh4/trace-events
+++ b/hw/sh4/trace-events
@@ -1,3 +1,3 @@
# sh7750.c
-sh7750_porta(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "porta changed from 0x%04x to 0x%04x\npdtra=0x%04x, pctra=0x%08x"
-sh7750_portb(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "portb changed from 0x%04x to 0x%04x\npdtrb=0x%04x, pctrb=0x%08x"
+sh7750_porta(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "porta changed from 0x%04x to 0x%04x (pdtra=0x%04x, pctra=0x%08x)"
+sh7750_portb(uint16_t prev, uint16_t cur, uint16_t pdtr, uint16_t pctr) "portb changed from 0x%04x to 0x%04x (pdtrb=0x%04x, pctrb=0x%08x)"
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 6e1a84c..49205ab 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -132,6 +132,9 @@
#define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */
#define FMC_WDT2_CTRL_EN BIT(0)
+/* DMA DRAM Side Address High Part (AST2700) */
+#define R_DMA_DRAM_ADDR_HIGH (0x7c / 4)
+
/* DMA Control/Status Register */
#define R_DMA_CTRL (0x80 / 4)
#define DMA_CTRL_REQUEST (1 << 31)
@@ -178,13 +181,18 @@
* DMA flash addresses should be 4 bytes aligned and the valid address
* range is 0x20000000 - 0x2FFFFFFF.
*
- * DMA length is from 4 bytes to 32MB
+ * DMA length is from 4 bytes to 32MB (AST2500)
* 0: 4 bytes
- * 0x7FFFFF: 32M bytes
+ * 0x1FFFFFC: 32M bytes
+ *
+ * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700)
+ * 0: 1 byte
+ * 0x1FFFFFF: 32M bytes
*/
#define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)
+#define DMA_DRAM_ADDR_HIGH(val) ((val) & 0xf)
#define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)
-#define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
+#define DMA_LENGTH(val) ((val) & 0x01FFFFFF)
/* Flash opcodes. */
#define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
@@ -203,6 +211,7 @@
#define ASPEED_SMC_FEATURE_DMA 0x1
#define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
#define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
+#define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08
static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)
{
@@ -214,6 +223,11 @@
return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL);
}
+static inline bool aspeed_smc_has_dma64(const AspeedSMCClass *asc)
+{
+ return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH);
+}
+
#define aspeed_smc_error(fmt, ...) \
qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__)
@@ -743,6 +757,8 @@
(aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||
(aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) ||
(aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) ||
+ (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) &&
+ addr == R_DMA_DRAM_ADDR_HIGH) ||
(aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) ||
(aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) ||
(addr >= R_SEG_ADDR0 &&
@@ -843,6 +859,19 @@
}
}
+static uint64_t aspeed_smc_dma_dram_addr(AspeedSMCState *s)
+{
+ return s->regs[R_DMA_DRAM_ADDR] |
+ ((uint64_t) s->regs[R_DMA_DRAM_ADDR_HIGH] << 32);
+}
+
+static uint32_t aspeed_smc_dma_len(AspeedSMCState *s)
+{
+ AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+
+ return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4);
+}
+
/*
* Accumulate the result of the reads to provide a checksum that will
* be used to validate the read timing settings.
@@ -850,6 +879,7 @@
static void aspeed_smc_dma_checksum(AspeedSMCState *s)
{
MemTxResult result;
+ uint32_t dma_len;
uint32_t data;
if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
@@ -861,7 +891,9 @@
aspeed_smc_dma_calibration(s);
}
- while (s->regs[R_DMA_LEN]) {
+ dma_len = aspeed_smc_dma_len(s);
+
+ while (dma_len) {
data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
@@ -877,7 +909,8 @@
*/
s->regs[R_DMA_CHECKSUM] += data;
s->regs[R_DMA_FLASH_ADDR] += 4;
- s->regs[R_DMA_LEN] -= 4;
+ dma_len -= 4;
+ s->regs[R_DMA_LEN] = dma_len;
}
if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
@@ -888,21 +921,34 @@
static void aspeed_smc_dma_rw(AspeedSMCState *s)
{
+ AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+ uint64_t dma_dram_offset;
+ uint64_t dma_dram_addr;
MemTxResult result;
+ uint32_t dma_len;
uint32_t data;
+ dma_len = aspeed_smc_dma_len(s);
+ dma_dram_addr = aspeed_smc_dma_dram_addr(s);
+
+ if (aspeed_smc_has_dma64(asc)) {
+ dma_dram_offset = dma_dram_addr - s->dram_base;
+ } else {
+ dma_dram_offset = dma_dram_addr;
+ }
+
trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?
"write" : "read",
s->regs[R_DMA_FLASH_ADDR],
- s->regs[R_DMA_DRAM_ADDR],
- s->regs[R_DMA_LEN]);
- while (s->regs[R_DMA_LEN]) {
+ dma_dram_offset,
+ dma_len);
+ while (dma_len) {
if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
- data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
+ data = address_space_ldl_le(&s->dram_as, dma_dram_offset,
MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
- aspeed_smc_error("DRAM read failed @%08x",
- s->regs[R_DMA_DRAM_ADDR]);
+ aspeed_smc_error("DRAM read failed @%" PRIx64,
+ dma_dram_offset);
return;
}
@@ -922,11 +968,11 @@
return;
}
- address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
+ address_space_stl_le(&s->dram_as, dma_dram_offset,
data, MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
- aspeed_smc_error("DRAM write failed @%08x",
- s->regs[R_DMA_DRAM_ADDR]);
+ aspeed_smc_error("DRAM write failed @%" PRIx64,
+ dma_dram_offset);
return;
}
}
@@ -935,9 +981,14 @@
* When the DMA is on-going, the DMA registers are updated
* with the current working addresses and length.
*/
+ dma_dram_offset += 4;
+ dma_dram_addr += 4;
+
+ s->regs[R_DMA_DRAM_ADDR_HIGH] = dma_dram_addr >> 32;
+ s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff;
s->regs[R_DMA_FLASH_ADDR] += 4;
- s->regs[R_DMA_DRAM_ADDR] += 4;
- s->regs[R_DMA_LEN] -= 4;
+ dma_len -= 4;
+ s->regs[R_DMA_LEN] = dma_len;
s->regs[R_DMA_CHECKSUM] += data;
}
}
@@ -1088,6 +1139,9 @@
} else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN &&
aspeed_smc_dma_granted(s)) {
s->regs[addr] = DMA_LENGTH(value);
+ } else if (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) &&
+ addr == R_DMA_DRAM_ADDR_HIGH) {
+ s->regs[addr] = DMA_DRAM_ADDR_HIGH(value);
} else {
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
__func__, addr);
@@ -1220,6 +1274,7 @@
static Property aspeed_smc_properties[] = {
DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
+ DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0),
DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
@@ -1261,7 +1316,7 @@
* Use the default segment value to size the memory region. This
* can be changed by FW at runtime.
*/
- memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
+ memory_region_init_io(&s->mmio, OBJECT(s), s->asc->reg_ops,
s, name, s->asc->segments[s->cs].size);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
}
@@ -1336,6 +1391,7 @@
asc->segment_to_reg = aspeed_smc_segment_to_reg;
asc->reg_to_segment = aspeed_smc_reg_to_segment;
asc->dma_ctrl = aspeed_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2400_smc_info = {
@@ -1381,10 +1437,12 @@
asc->features = ASPEED_SMC_FEATURE_DMA;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x1FFFFFFC;
+ asc->dma_start_length = 4;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_smc_segment_to_reg;
asc->reg_to_segment = aspeed_smc_reg_to_segment;
asc->dma_ctrl = aspeed_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2400_fmc_info = {
@@ -1424,6 +1482,7 @@
asc->reg_to_segment = aspeed_smc_reg_to_segment;
asc->dma_ctrl = aspeed_smc_dma_ctrl;
asc->addr_width = aspeed_2400_spi1_addr_width;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2400_spi1_info = {
@@ -1448,7 +1507,7 @@
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
- dc->desc = "Aspeed 2600 FMC Controller";
+ dc->desc = "Aspeed 2500 FMC Controller";
asc->r_conf = R_CONF;
asc->r_ce_ctrl = R_CE_CTRL;
asc->r_ctrl0 = R_CTRL0;
@@ -1464,10 +1523,12 @@
asc->features = ASPEED_SMC_FEATURE_DMA;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x3FFFFFFC;
+ asc->dma_start_length = 4;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_smc_segment_to_reg;
asc->reg_to_segment = aspeed_smc_reg_to_segment;
asc->dma_ctrl = aspeed_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2500_fmc_info = {
@@ -1486,7 +1547,7 @@
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
- dc->desc = "Aspeed 2600 SPI1 Controller";
+ dc->desc = "Aspeed 2500 SPI1 Controller";
asc->r_conf = R_CONF;
asc->r_ce_ctrl = R_CE_CTRL;
asc->r_ctrl0 = R_CTRL0;
@@ -1503,6 +1564,7 @@
asc->segment_to_reg = aspeed_smc_segment_to_reg;
asc->reg_to_segment = aspeed_smc_reg_to_segment;
asc->dma_ctrl = aspeed_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2500_spi1_info = {
@@ -1521,7 +1583,7 @@
DeviceClass *dc = DEVICE_CLASS(klass);
AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
- dc->desc = "Aspeed 2600 SPI2 Controller";
+ dc->desc = "Aspeed 2500 SPI2 Controller";
asc->r_conf = R_CONF;
asc->r_ce_ctrl = R_CE_CTRL;
asc->r_ctrl0 = R_CTRL0;
@@ -1538,6 +1600,7 @@
asc->segment_to_reg = aspeed_smc_segment_to_reg;
asc->reg_to_segment = aspeed_smc_reg_to_segment;
asc->dma_ctrl = aspeed_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2500_spi2_info = {
@@ -1620,10 +1683,12 @@
ASPEED_SMC_FEATURE_WDT_CONTROL;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x3FFFFFFC;
+ asc->dma_start_length = 1;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2600_fmc_info = {
@@ -1658,10 +1723,12 @@
ASPEED_SMC_FEATURE_DMA_GRANT;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x3FFFFFFC;
+ asc->dma_start_length = 1;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2600_spi1_info = {
@@ -1697,10 +1764,12 @@
ASPEED_SMC_FEATURE_DMA_GRANT;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x3FFFFFFC;
+ asc->dma_start_length = 1;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_2600_spi2_info = {
@@ -1778,10 +1847,12 @@
asc->features = ASPEED_SMC_FEATURE_DMA;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x000BFFFC;
+ asc->dma_start_length = 1;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_1030_smc_segment_to_reg;
asc->reg_to_segment = aspeed_1030_smc_reg_to_segment;
asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_1030_fmc_info = {
@@ -1815,10 +1886,12 @@
asc->features = ASPEED_SMC_FEATURE_DMA;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x000BFFFC;
+ asc->dma_start_length = 1;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_1030_spi1_info = {
@@ -1851,10 +1924,12 @@
asc->features = ASPEED_SMC_FEATURE_DMA;
asc->dma_flash_mask = 0x0FFFFFFC;
asc->dma_dram_mask = 0x000BFFFC;
+ asc->dma_start_length = 1;
asc->nregs = ASPEED_SMC_R_MAX;
asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_smc_flash_ops;
}
static const TypeInfo aspeed_1030_spi2_info = {
@@ -1863,6 +1938,234 @@
.class_init = aspeed_1030_spi2_class_init,
};
+/*
+ * The FMC Segment Registers of the AST2700 have a 64KB unit.
+ * Only bits [31:16] are used for decoding.
+ */
+#define AST2700_SEG_ADDR_MASK 0xffff0000
+
+static uint32_t aspeed_2700_smc_segment_to_reg(const AspeedSMCState *s,
+ const AspeedSegments *seg)
+{
+ uint32_t reg = 0;
+
+ /* Disabled segments have a nil register */
+ if (!seg->size) {
+ return 0;
+ }
+
+ reg |= (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */
+ reg |= (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end offset */
+ return reg;
+}
+
+static void aspeed_2700_smc_reg_to_segment(const AspeedSMCState *s,
+ uint32_t reg, AspeedSegments *seg)
+{
+ uint32_t start_offset = (reg << 16) & AST2700_SEG_ADDR_MASK;
+ uint32_t end_offset = reg & AST2700_SEG_ADDR_MASK;
+ AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+
+ if (reg) {
+ seg->addr = asc->flash_window_base + start_offset;
+ seg->size = end_offset + (64 * KiB) - start_offset;
+ } else {
+ seg->addr = asc->flash_window_base;
+ seg->size = 0;
+ }
+}
+
+static const uint32_t aspeed_2700_fmc_resets[ASPEED_SMC_R_MAX] = {
+ [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
+ CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
+ [R_CE_CTRL] = 0x0000aa00,
+ [R_CTRL0] = 0x406b0641,
+ [R_CTRL1] = 0x00000400,
+ [R_CTRL2] = 0x00000400,
+ [R_CTRL3] = 0x00000400,
+ [R_SEG_ADDR0] = 0x08000000,
+ [R_SEG_ADDR1] = 0x10000800,
+ [R_SEG_ADDR2] = 0x00000000,
+ [R_SEG_ADDR3] = 0x00000000,
+ [R_DUMMY_DATA] = 0x00010000,
+ [R_DMA_DRAM_ADDR_HIGH] = 0x00000000,
+ [R_TIMINGS] = 0x007b0000,
+};
+
+static const MemoryRegionOps aspeed_2700_smc_flash_ops = {
+ .read = aspeed_smc_flash_read,
+ .write = aspeed_smc_flash_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
+static const AspeedSegments aspeed_2700_fmc_segments[] = {
+ { 0x0, 128 * MiB }, /* start address is readonly */
+ { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
+ { 256 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
+ { 0x0, 0 }, /* disabled */
+};
+
+static void aspeed_2700_fmc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
+
+ dc->desc = "Aspeed 2700 FMC Controller";
+ asc->r_conf = R_CONF;
+ asc->r_ce_ctrl = R_CE_CTRL;
+ asc->r_ctrl0 = R_CTRL0;
+ asc->r_timings = R_TIMINGS;
+ asc->nregs_timings = 3;
+ asc->conf_enable_w0 = CONF_ENABLE_W0;
+ asc->cs_num_max = 3;
+ asc->segments = aspeed_2700_fmc_segments;
+ asc->segment_addr_mask = 0xffffffff;
+ asc->resets = aspeed_2700_fmc_resets;
+ asc->flash_window_base = 0x100000000;
+ asc->flash_window_size = 1 * GiB;
+ asc->features = ASPEED_SMC_FEATURE_DMA |
+ ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
+ asc->dma_flash_mask = 0x2FFFFFFC;
+ asc->dma_dram_mask = 0xFFFFFFFC;
+ asc->dma_start_length = 1;
+ asc->nregs = ASPEED_SMC_R_MAX;
+ asc->segment_to_reg = aspeed_2700_smc_segment_to_reg;
+ asc->reg_to_segment = aspeed_2700_smc_reg_to_segment;
+ asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_2700_smc_flash_ops;
+}
+
+static const TypeInfo aspeed_2700_fmc_info = {
+ .name = "aspeed.fmc-ast2700",
+ .parent = TYPE_ASPEED_SMC,
+ .class_init = aspeed_2700_fmc_class_init,
+};
+
+static const AspeedSegments aspeed_2700_spi0_segments[] = {
+ { 0x0, 128 * MiB }, /* start address is readonly */
+ { 128 * MiB, 128 * MiB }, /* start address is readonly */
+ { 0x0, 0 }, /* disabled */
+};
+
+static void aspeed_2700_spi0_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
+
+ dc->desc = "Aspeed 2700 SPI0 Controller";
+ asc->r_conf = R_CONF;
+ asc->r_ce_ctrl = R_CE_CTRL;
+ asc->r_ctrl0 = R_CTRL0;
+ asc->r_timings = R_TIMINGS;
+ asc->nregs_timings = 2;
+ asc->conf_enable_w0 = CONF_ENABLE_W0;
+ asc->cs_num_max = 2;
+ asc->segments = aspeed_2700_spi0_segments;
+ asc->segment_addr_mask = 0xffffffff;
+ asc->flash_window_base = 0x180000000;
+ asc->flash_window_size = 1 * GiB;
+ asc->features = ASPEED_SMC_FEATURE_DMA |
+ ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
+ asc->dma_flash_mask = 0x2FFFFFFC;
+ asc->dma_dram_mask = 0xFFFFFFFC;
+ asc->dma_start_length = 1;
+ asc->nregs = ASPEED_SMC_R_MAX;
+ asc->segment_to_reg = aspeed_2700_smc_segment_to_reg;
+ asc->reg_to_segment = aspeed_2700_smc_reg_to_segment;
+ asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_2700_smc_flash_ops;
+}
+
+static const TypeInfo aspeed_2700_spi0_info = {
+ .name = "aspeed.spi0-ast2700",
+ .parent = TYPE_ASPEED_SMC,
+ .class_init = aspeed_2700_spi0_class_init,
+};
+
+static const AspeedSegments aspeed_2700_spi1_segments[] = {
+ { 0x0, 128 * MiB }, /* start address is readonly */
+ { 0x0, 0 }, /* disabled */
+};
+
+static void aspeed_2700_spi1_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
+
+ dc->desc = "Aspeed 2700 SPI1 Controller";
+ asc->r_conf = R_CONF;
+ asc->r_ce_ctrl = R_CE_CTRL;
+ asc->r_ctrl0 = R_CTRL0;
+ asc->r_timings = R_TIMINGS;
+ asc->nregs_timings = 2;
+ asc->conf_enable_w0 = CONF_ENABLE_W0;
+ asc->cs_num_max = 2;
+ asc->segments = aspeed_2700_spi1_segments;
+ asc->segment_addr_mask = 0xffffffff;
+ asc->flash_window_base = 0x200000000;
+ asc->flash_window_size = 1 * GiB;
+ asc->features = ASPEED_SMC_FEATURE_DMA |
+ ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
+ asc->dma_flash_mask = 0x2FFFFFFC;
+ asc->dma_dram_mask = 0xFFFFFFFC;
+ asc->dma_start_length = 1;
+ asc->nregs = ASPEED_SMC_R_MAX;
+ asc->segment_to_reg = aspeed_2700_smc_segment_to_reg;
+ asc->reg_to_segment = aspeed_2700_smc_reg_to_segment;
+ asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_2700_smc_flash_ops;
+}
+
+static const TypeInfo aspeed_2700_spi1_info = {
+ .name = "aspeed.spi1-ast2700",
+ .parent = TYPE_ASPEED_SMC,
+ .class_init = aspeed_2700_spi1_class_init,
+};
+
+static const AspeedSegments aspeed_2700_spi2_segments[] = {
+ { 0x0, 128 * MiB }, /* start address is readonly */
+ { 0x0, 0 }, /* disabled */
+};
+
+static void aspeed_2700_spi2_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
+
+ dc->desc = "Aspeed 2700 SPI2 Controller";
+ asc->r_conf = R_CONF;
+ asc->r_ce_ctrl = R_CE_CTRL;
+ asc->r_ctrl0 = R_CTRL0;
+ asc->r_timings = R_TIMINGS;
+ asc->nregs_timings = 2;
+ asc->conf_enable_w0 = CONF_ENABLE_W0;
+ asc->cs_num_max = 2;
+ asc->segments = aspeed_2700_spi2_segments;
+ asc->segment_addr_mask = 0xffffffff;
+ asc->flash_window_base = 0x280000000;
+ asc->flash_window_size = 1 * GiB;
+ asc->features = ASPEED_SMC_FEATURE_DMA |
+ ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;
+ asc->dma_flash_mask = 0x0FFFFFFC;
+ asc->dma_dram_mask = 0xFFFFFFFC;
+ asc->dma_start_length = 1;
+ asc->nregs = ASPEED_SMC_R_MAX;
+ asc->segment_to_reg = aspeed_2700_smc_segment_to_reg;
+ asc->reg_to_segment = aspeed_2700_smc_reg_to_segment;
+ asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
+ asc->reg_ops = &aspeed_2700_smc_flash_ops;
+}
+
+static const TypeInfo aspeed_2700_spi2_info = {
+ .name = "aspeed.spi2-ast2700",
+ .parent = TYPE_ASPEED_SMC,
+ .class_init = aspeed_2700_spi2_class_init,
+};
+
static void aspeed_smc_register_types(void)
{
type_register_static(&aspeed_smc_flash_info);
@@ -1879,6 +2182,10 @@
type_register_static(&aspeed_1030_fmc_info);
type_register_static(&aspeed_1030_spi1_info);
type_register_static(&aspeed_1030_spi2_info);
+ type_register_static(&aspeed_2700_fmc_info);
+ type_register_static(&aspeed_2700_spi0_info);
+ type_register_static(&aspeed_2700_spi1_info);
+ type_register_static(&aspeed_2700_spi2_info);
}
type_init(aspeed_smc_register_types)
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index 2d5bd2b..7b5ad6a 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -6,7 +6,7 @@
aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
-aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x"
+aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint64_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%" PRIx64 " size:0x%08x"
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
diff --git a/hw/usb/trace-events b/hw/usb/trace-events
index fd7b90d..4673271 100644
--- a/hw/usb/trace-events
+++ b/hw/usb/trace-events
@@ -15,7 +15,7 @@
# hcd-ohci.c
usb_ohci_iso_td_read_failed(uint32_t addr) "ISO_TD read error at 0x%x"
-usb_ohci_iso_td_head(uint32_t head, uint32_t tail, uint32_t flags, uint32_t bp, uint32_t next, uint32_t be, uint32_t framenum, uint32_t startframe, uint32_t framecount, int rel_frame_num) "ISO_TD ED head 0x%.8x tailp 0x%.8x\n0x%.8x 0x%.8x 0x%.8x 0x%.8x\nframe_number 0x%.8x starting_frame 0x%.8x\nframe_count 0x%.8x relative %d"
+usb_ohci_iso_td_head(uint32_t head, uint32_t tail, uint32_t flags, uint32_t bp, uint32_t next, uint32_t be, uint32_t framenum, uint32_t startframe, uint32_t framecount, int rel_frame_num) "ISO_TD ED head 0x%.8x tailp 0x%.8x, flags 0x%.8x bp 0x%.8x next 0x%.8x be 0x%.8x, frame_number 0x%.8x starting_frame 0x%.8x, frame_count 0x%.8x relative %d"
usb_ohci_iso_td_head_offset(uint32_t o0, uint32_t o1, uint32_t o2, uint32_t o3, uint32_t o4, uint32_t o5, uint32_t o6, uint32_t o7) "0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x"
usb_ohci_iso_td_relative_frame_number_neg(int rel) "ISO_TD R=%d < 0"
usb_ohci_iso_td_relative_frame_number_big(int rel, int count) "ISO_TD R=%d > FC=%d"
@@ -23,7 +23,7 @@
usb_ohci_iso_td_bad_bp_be(uint32_t bp, uint32_t be) "ISO_TD bp 0x%.8x be 0x%.8x"
usb_ohci_iso_td_bad_cc_not_accessed(uint32_t start, uint32_t next) "ISO_TD cc != not accessed 0x%.8x 0x%.8x"
usb_ohci_iso_td_bad_cc_overrun(uint32_t start, uint32_t next) "ISO_TD start_offset=0x%.8x > next_offset=0x%.8x"
-usb_ohci_iso_td_so(uint32_t so, uint32_t eo, uint32_t s, uint32_t e, const char *str, ssize_t len, int ret) "0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d"
+usb_ohci_iso_td_so(uint32_t so, uint32_t eo, uint32_t s, uint32_t e, const char *str, ssize_t len, int ret) "0x%.8x eo 0x%.8x sa 0x%.8x ea 0x%.8x dir %s len %zu ret %d"
usb_ohci_iso_td_data_overrun(int ret, ssize_t len) "DataOverrun %d > %zu"
usb_ohci_iso_td_data_underrun(int ret) "DataUnderrun %d"
usb_ohci_iso_td_nak(int ret) "got NAK/STALL %d"
@@ -55,7 +55,7 @@
usb_ohci_td_too_many_pending(int ep) "ep=%d"
usb_ohci_td_packet_status(int status) "status=%d"
usb_ohci_ed_read_error(uint32_t addr) "ED read error at 0x%x"
-usb_ohci_ed_pkt(uint32_t cur, int h, int c, uint32_t head, uint32_t tail, uint32_t next) "ED @ 0x%.8x h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x"
+usb_ohci_ed_pkt(uint32_t cur, int h, int c, uint32_t head, uint32_t tail, uint32_t next) "ED @ 0x%.8x h=%u c=%u head=0x%.8x tailp=0x%.8x next=0x%.8x"
usb_ohci_ed_pkt_flags(uint32_t fa, uint32_t en, uint32_t d, int s, int k, int f, uint32_t mps) "fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u"
usb_ohci_hcca_read_error(uint32_t addr) "HCCA read error at 0x%x"
usb_ohci_mem_read(uint32_t size, const char *name, uint32_t addr, uint32_t offs, uint32_t val) "%d %s 0x%x %d -> 0x%x"
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index 64161bf..e16179b 100644
--- a/hw/vfio/trace-events
+++ b/hw/vfio/trace-events
@@ -19,7 +19,7 @@
vfio_msix_relo(const char *name, int bar, uint64_t offset) " (%s) BAR %d offset 0x%"PRIx64""
vfio_msi_enable(const char *name, int nr_vectors) " (%s) Enabled %d MSI vectors"
vfio_msi_disable(const char *name) " (%s)"
-vfio_pci_load_rom(const char *name, unsigned long size, unsigned long offset, unsigned long flags) "Device %s ROM:\n size: 0x%lx, offset: 0x%lx, flags: 0x%lx"
+vfio_pci_load_rom(const char *name, unsigned long size, unsigned long offset, unsigned long flags) "Device '%s' ROM: size: 0x%lx, offset: 0x%lx, flags: 0x%lx"
vfio_rom_read(const char *name, uint64_t addr, int size, uint64_t data) " (%s, 0x%"PRIx64", 0x%x) = 0x%"PRIx64
vfio_pci_size_rom(const char *name, int size) "%s ROM size 0x%x"
vfio_vga_write(uint64_t addr, uint64_t data, int size) " (0x%"PRIx64", 0x%"PRIx64", %d)"
@@ -35,7 +35,7 @@
vfio_pci_hot_reset_has_dep_devices(const char *name) "%s: hot reset dependent devices:"
vfio_pci_hot_reset_dep_devices(int domain, int bus, int slot, int function, int group_id) "\t%04x:%02x:%02x.%x group %d"
vfio_pci_hot_reset_result(const char *name, const char *result) "%s hot reset: %s"
-vfio_populate_device_config(const char *name, unsigned long size, unsigned long offset, unsigned long flags) "Device %s config:\n size: 0x%lx, offset: 0x%lx, flags: 0x%lx"
+vfio_populate_device_config(const char *name, unsigned long size, unsigned long offset, unsigned long flags) "Device '%s' config: size: 0x%lx, offset: 0x%lx, flags: 0x%lx"
vfio_populate_device_get_irq_info_failure(const char *errstr) "VFIO_DEVICE_GET_IRQ_INFO failure: %s"
vfio_attach_device(const char *name, int group_id) " (%s) group %d"
vfio_detach_device(const char *name, int group_id) " (%s) group %d"
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index d70b656..75685c5 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -422,12 +422,36 @@
.class_init = aspeed_1030_wdt_class_init,
};
+static void aspeed_2700_wdt_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 Watchdog Controller";
+ awc->iosize = 0x80;
+ awc->ext_pulse_width_mask = 0xfffff; /* TODO */
+ awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
+ awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
+ awc->wdt_reload = aspeed_wdt_reload_1mhz;
+ awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
+ awc->default_status = 0x014FB180;
+ awc->default_reload_value = 0x014FB180;
+}
+
+static const TypeInfo aspeed_2700_wdt_info = {
+ .name = TYPE_ASPEED_2700_WDT,
+ .parent = TYPE_ASPEED_WDT,
+ .instance_size = sizeof(AspeedWDTState),
+ .class_init = aspeed_2700_wdt_class_init,
+};
+
static void wdt_aspeed_register_types(void)
{
type_register_static(&aspeed_wdt_info);
type_register_static(&aspeed_2400_wdt_info);
type_register_static(&aspeed_2500_wdt_info);
type_register_static(&aspeed_2600_wdt_info);
+ type_register_static(&aspeed_2700_wdt_info);
type_register_static(&aspeed_1030_wdt_info);
}
diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c
index a0a0252..b8ace1c 100644
--- a/hw/xen/xen-hvm-common.c
+++ b/hw/xen/xen-hvm-common.c
@@ -10,12 +10,18 @@
#include "hw/boards.h"
#include "hw/xen/arch_hvm.h"
-MemoryRegion xen_memory;
+MemoryRegion xen_memory, xen_grants;
-/* Check for xen memory. */
+/* Check for any kind of xen memory, foreign mappings or grants. */
bool xen_mr_is_memory(MemoryRegion *mr)
{
- return mr == &xen_memory;
+ return mr == &xen_memory || mr == &xen_grants;
+}
+
+/* Check specifically for grants. */
+bool xen_mr_is_grants(MemoryRegion *mr)
+{
+ return mr == &xen_grants;
}
void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size, MemoryRegion *mr,
diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c
index fa6813b..5f23b0a 100644
--- a/hw/xen/xen-mapcache.c
+++ b/hw/xen/xen-mapcache.c
@@ -14,6 +14,7 @@
#include <sys/resource.h>
+#include "hw/xen/xen-hvm-common.h"
#include "hw/xen/xen_native.h"
#include "qemu/bitmap.h"
@@ -21,15 +22,14 @@
#include "sysemu/xen-mapcache.h"
#include "trace.h"
+#include <xenevtchn.h>
+#include <xengnttab.h>
#if HOST_LONG_BITS == 32
-# define MCACHE_BUCKET_SHIFT 16
# define MCACHE_MAX_SIZE (1UL<<31) /* 2GB Cap */
#else
-# define MCACHE_BUCKET_SHIFT 20
# define MCACHE_MAX_SIZE (1UL<<35) /* 32GB Cap */
#endif
-#define MCACHE_BUCKET_SIZE (1UL << MCACHE_BUCKET_SHIFT)
/* This is the size of the virtual address space reserve to QEMU that will not
* be use by MapCache.
@@ -44,6 +44,7 @@
unsigned long *valid_mapping;
uint32_t lock;
#define XEN_MAPCACHE_ENTRY_DUMMY (1 << 0)
+#define XEN_MAPCACHE_ENTRY_GRANT (1 << 1)
uint8_t flags;
hwaddr size;
struct MapCacheEntry *next;
@@ -65,7 +66,8 @@
/* For most cases (>99.9%), the page address is the same. */
MapCacheEntry *last_entry;
unsigned long max_mcache_size;
- unsigned int mcache_bucket_shift;
+ unsigned int bucket_shift;
+ unsigned long bucket_size;
phys_offset_to_gaddr_t phys_offset_to_gaddr;
QemuMutex lock;
@@ -73,6 +75,8 @@
} MapCache;
static MapCache *mapcache;
+static MapCache *mapcache_grants;
+static xengnttab_handle *xen_region_gnttabdev;
static inline void mapcache_lock(MapCache *mc)
{
@@ -95,11 +99,14 @@
static MapCache *xen_map_cache_init_single(phys_offset_to_gaddr_t f,
void *opaque,
+ unsigned int bucket_shift,
unsigned long max_size)
{
unsigned long size;
MapCache *mc;
+ assert(bucket_shift >= XC_PAGE_SHIFT);
+
mc = g_new0(MapCache, 1);
mc->phys_offset_to_gaddr = f;
@@ -108,12 +115,14 @@
QTAILQ_INIT(&mc->locked_entries);
+ mc->bucket_shift = bucket_shift;
+ mc->bucket_size = 1UL << bucket_shift;
mc->max_mcache_size = max_size;
mc->nr_buckets =
(((mc->max_mcache_size >> XC_PAGE_SHIFT) +
- (1UL << (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)) - 1) >>
- (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT));
+ (1UL << (bucket_shift - XC_PAGE_SHIFT)) - 1) >>
+ (bucket_shift - XC_PAGE_SHIFT));
size = mc->nr_buckets * sizeof(MapCacheEntry);
size = (size + XC_PAGE_SIZE - 1) & ~(XC_PAGE_SIZE - 1);
@@ -126,6 +135,19 @@
{
struct rlimit rlimit_as;
unsigned long max_mcache_size;
+ unsigned int bucket_shift;
+
+ xen_region_gnttabdev = xengnttab_open(NULL, 0);
+ if (xen_region_gnttabdev == NULL) {
+ error_report("mapcache: Failed to open gnttab device");
+ exit(EXIT_FAILURE);
+ }
+
+ if (HOST_LONG_BITS == 32) {
+ bucket_shift = 16;
+ } else {
+ bucket_shift = 20;
+ }
if (geteuid() == 0) {
rlimit_as.rlim_cur = RLIM_INFINITY;
@@ -146,7 +168,18 @@
}
}
- mapcache = xen_map_cache_init_single(f, opaque, max_mcache_size);
+ mapcache = xen_map_cache_init_single(f, opaque,
+ bucket_shift,
+ max_mcache_size);
+
+ /*
+ * Grant mappings must use XC_PAGE_SIZE granularity since we can't
+ * map anything beyond the number of pages granted to us.
+ */
+ mapcache_grants = xen_map_cache_init_single(f, opaque,
+ XC_PAGE_SHIFT,
+ max_mcache_size);
+
setrlimit(RLIMIT_AS, &rlimit_as);
}
@@ -155,17 +188,25 @@
void *vaddr,
hwaddr size,
hwaddr address_index,
- bool dummy)
+ bool dummy,
+ bool grant,
+ bool is_write,
+ ram_addr_t ram_offset)
{
uint8_t *vaddr_base;
- xen_pfn_t *pfns;
- int *err;
+ g_autofree uint32_t *refs = NULL;
+ g_autofree xen_pfn_t *pfns = NULL;
+ g_autofree int *err;
unsigned int i;
hwaddr nb_pfn = size >> XC_PAGE_SHIFT;
trace_xen_remap_bucket(address_index);
- pfns = g_new0(xen_pfn_t, nb_pfn);
+ if (grant) {
+ refs = g_new0(uint32_t, nb_pfn);
+ } else {
+ pfns = g_new0(xen_pfn_t, nb_pfn);
+ }
err = g_new0(int, nb_pfn);
if (entry->vaddr_base != NULL) {
@@ -194,21 +235,51 @@
g_free(entry->valid_mapping);
entry->valid_mapping = NULL;
- for (i = 0; i < nb_pfn; i++) {
- pfns[i] = (address_index << (MCACHE_BUCKET_SHIFT-XC_PAGE_SHIFT)) + i;
+ if (grant) {
+ hwaddr grant_base = address_index - (ram_offset >> XC_PAGE_SHIFT);
+
+ for (i = 0; i < nb_pfn; i++) {
+ refs[i] = grant_base + i;
+ }
+ } else {
+ for (i = 0; i < nb_pfn; i++) {
+ pfns[i] = (address_index << (mc->bucket_shift - XC_PAGE_SHIFT)) + i;
+ }
}
- /*
- * If the caller has requested the mapping at a specific address use
- * MAP_FIXED to make sure it's honored.
- */
+ entry->flags &= ~XEN_MAPCACHE_ENTRY_GRANT;
+
if (!dummy) {
- vaddr_base = xenforeignmemory_map2(xen_fmem, xen_domid, vaddr,
- PROT_READ | PROT_WRITE,
- vaddr ? MAP_FIXED : 0,
- nb_pfn, pfns, err);
+ if (grant) {
+ int prot = PROT_READ;
+
+ if (is_write) {
+ prot |= PROT_WRITE;
+ }
+
+ entry->flags |= XEN_MAPCACHE_ENTRY_GRANT;
+ assert(vaddr == NULL);
+ vaddr_base = xengnttab_map_domain_grant_refs(xen_region_gnttabdev,
+ nb_pfn,
+ xen_domid, refs,
+ prot);
+ } else {
+ /*
+ * If the caller has requested the mapping at a specific address use
+ * MAP_FIXED to make sure it's honored.
+ *
+ * We don't yet support upgrading mappings from RO to RW, to handle
+ * models using ordinary address_space_rw(), foreign mappings ignore
+ * is_write and are always mapped RW.
+ */
+ vaddr_base = xenforeignmemory_map2(xen_fmem, xen_domid, vaddr,
+ PROT_READ | PROT_WRITE,
+ vaddr ? MAP_FIXED : 0,
+ nb_pfn, pfns, err);
+ }
if (vaddr_base == NULL) {
- perror("xenforeignmemory_map2");
+ perror(grant ? "xengnttab_map_domain_grant_refs"
+ : "xenforeignmemory_map2");
exit(-1);
}
} else {
@@ -247,14 +318,13 @@
bitmap_set(entry->valid_mapping, i, 1);
}
}
-
- g_free(pfns);
- g_free(err);
}
static uint8_t *xen_map_cache_unlocked(MapCache *mc,
hwaddr phys_addr, hwaddr size,
- uint8_t lock, bool dma, bool is_write)
+ ram_addr_t ram_offset,
+ uint8_t lock, bool dma,
+ bool grant, bool is_write)
{
MapCacheEntry *entry, *pentry = NULL,
*free_entry = NULL, *free_pentry = NULL;
@@ -266,8 +336,8 @@
bool dummy = false;
tryagain:
- address_index = phys_addr >> MCACHE_BUCKET_SHIFT;
- address_offset = phys_addr & (MCACHE_BUCKET_SIZE - 1);
+ address_index = phys_addr >> mc->bucket_shift;
+ address_offset = phys_addr & (mc->bucket_size - 1);
trace_xen_map_cache(phys_addr);
@@ -294,14 +364,14 @@
return mc->last_entry->vaddr_base + address_offset;
}
- /* size is always a multiple of MCACHE_BUCKET_SIZE */
+ /* size is always a multiple of mc->bucket_size */
if (size) {
cache_size = size + address_offset;
- if (cache_size % MCACHE_BUCKET_SIZE) {
- cache_size += MCACHE_BUCKET_SIZE - (cache_size % MCACHE_BUCKET_SIZE);
+ if (cache_size % mc->bucket_size) {
+ cache_size += mc->bucket_size - (cache_size % mc->bucket_size);
}
} else {
- cache_size = MCACHE_BUCKET_SIZE;
+ cache_size = mc->bucket_size;
}
entry = &mc->entry[address_index % mc->nr_buckets];
@@ -325,14 +395,16 @@
if (!entry) {
entry = g_new0(MapCacheEntry, 1);
pentry->next = entry;
- xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy);
+ xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy,
+ grant, is_write, ram_offset);
} else if (!entry->lock) {
if (!entry->vaddr_base || entry->paddr_index != address_index ||
entry->size != cache_size ||
!test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
entry->valid_mapping)) {
- xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy);
+ xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy,
+ grant, is_write, ram_offset);
}
}
@@ -379,14 +451,30 @@
uint8_t *xen_map_cache(MemoryRegion *mr,
hwaddr phys_addr, hwaddr size,
+ ram_addr_t ram_addr_offset,
uint8_t lock, bool dma,
bool is_write)
{
+ bool grant = xen_mr_is_grants(mr);
+ MapCache *mc = grant ? mapcache_grants : mapcache;
uint8_t *p;
- mapcache_lock(mapcache);
- p = xen_map_cache_unlocked(mapcache, phys_addr, size, lock, dma, is_write);
- mapcache_unlock(mapcache);
+ if (grant && !lock) {
+ /*
+ * Grants are only supported via address_space_map(). Anything
+ * else is considered a user/guest error.
+ *
+ * QEMU generally doesn't expect these mappings to ever fail, so
+ * if this happens we report an error message and abort().
+ */
+ error_report("Tried to access a grant reference without mapping it.");
+ abort();
+ }
+
+ mapcache_lock(mc);
+ p = xen_map_cache_unlocked(mc, phys_addr, size, ram_addr_offset,
+ lock, dma, grant, is_write);
+ mapcache_unlock(mc);
return p;
}
@@ -422,7 +510,7 @@
trace_xen_ram_addr_from_mapcache_not_in_cache(ptr);
raddr = RAM_ADDR_INVALID;
} else {
- raddr = (reventry->paddr_index << MCACHE_BUCKET_SHIFT) +
+ raddr = (reventry->paddr_index << mc->bucket_shift) +
((unsigned long) ptr - (unsigned long) entry->vaddr_base);
}
mapcache_unlock(mc);
@@ -431,7 +519,14 @@
ram_addr_t xen_ram_addr_from_mapcache(void *ptr)
{
- return xen_ram_addr_from_mapcache_single(mapcache, ptr);
+ ram_addr_t addr;
+
+ addr = xen_ram_addr_from_mapcache_single(mapcache, ptr);
+ if (addr == RAM_ADDR_INVALID) {
+ addr = xen_ram_addr_from_mapcache_single(mapcache_grants, ptr);
+ }
+
+ return addr;
}
static void xen_invalidate_map_cache_entry_unlocked(MapCache *mc,
@@ -442,6 +537,7 @@
hwaddr paddr_index;
hwaddr size;
int found = 0;
+ int rc;
QTAILQ_FOREACH(reventry, &mc->locked_entries, next) {
if (reventry->vaddr_req == buffer) {
@@ -479,18 +575,30 @@
return;
}
entry->lock--;
- if (entry->lock > 0 || pentry == NULL) {
+ if (entry->lock > 0) {
return;
}
- pentry->next = entry->next;
ram_block_notify_remove(entry->vaddr_base, entry->size, entry->size);
- if (munmap(entry->vaddr_base, entry->size) != 0) {
+ if (entry->flags & XEN_MAPCACHE_ENTRY_GRANT) {
+ rc = xengnttab_unmap(xen_region_gnttabdev, entry->vaddr_base,
+ entry->size >> mc->bucket_shift);
+ } else {
+ rc = munmap(entry->vaddr_base, entry->size);
+ }
+
+ if (rc) {
perror("unmap fails");
exit(-1);
}
+
g_free(entry->valid_mapping);
- g_free(entry);
+ if (pentry) {
+ pentry->next = entry->next;
+ g_free(entry);
+ } else {
+ memset(entry, 0, sizeof *entry);
+ }
}
typedef struct XenMapCacheData {
@@ -498,14 +606,24 @@
uint8_t *buffer;
} XenMapCacheData;
+static void xen_invalidate_map_cache_entry_single(MapCache *mc, uint8_t *buffer)
+{
+ mapcache_lock(mc);
+ xen_invalidate_map_cache_entry_unlocked(mc, buffer);
+ mapcache_unlock(mc);
+}
+
+static void xen_invalidate_map_cache_entry_all(uint8_t *buffer)
+{
+ xen_invalidate_map_cache_entry_single(mapcache, buffer);
+ xen_invalidate_map_cache_entry_single(mapcache_grants, buffer);
+}
+
static void xen_invalidate_map_cache_entry_bh(void *opaque)
{
XenMapCacheData *data = opaque;
- mapcache_lock(mapcache);
- xen_invalidate_map_cache_entry_unlocked(mapcache, data->buffer);
- mapcache_unlock(mapcache);
-
+ xen_invalidate_map_cache_entry_all(data->buffer);
aio_co_wake(data->co);
}
@@ -520,9 +638,7 @@
xen_invalidate_map_cache_entry_bh, &data);
qemu_coroutine_yield();
} else {
- mapcache_lock(mapcache);
- xen_invalidate_map_cache_entry_unlocked(mapcache, buffer);
- mapcache_unlock(mapcache);
+ xen_invalidate_map_cache_entry_all(buffer);
}
}
@@ -574,6 +690,7 @@
bdrv_drain_all();
xen_invalidate_map_cache_single(mapcache);
+ xen_invalidate_map_cache_single(mapcache_grants);
}
static uint8_t *xen_replace_cache_entry_unlocked(MapCache *mc,
@@ -585,8 +702,8 @@
hwaddr address_index, address_offset;
hwaddr test_bit_size, cache_size = size;
- address_index = old_phys_addr >> MCACHE_BUCKET_SHIFT;
- address_offset = old_phys_addr & (MCACHE_BUCKET_SIZE - 1);
+ address_index = old_phys_addr >> mc->bucket_shift;
+ address_offset = old_phys_addr & (mc->bucket_size - 1);
assert(size);
/* test_bit_size is always a multiple of XC_PAGE_SIZE */
@@ -595,8 +712,8 @@
test_bit_size += XC_PAGE_SIZE - (test_bit_size % XC_PAGE_SIZE);
}
cache_size = size + address_offset;
- if (cache_size % MCACHE_BUCKET_SIZE) {
- cache_size += MCACHE_BUCKET_SIZE - (cache_size % MCACHE_BUCKET_SIZE);
+ if (cache_size % mc->bucket_size) {
+ cache_size += mc->bucket_size - (cache_size % mc->bucket_size);
}
entry = &mc->entry[address_index % mc->nr_buckets];
@@ -609,13 +726,16 @@
return NULL;
}
- address_index = new_phys_addr >> MCACHE_BUCKET_SHIFT;
- address_offset = new_phys_addr & (MCACHE_BUCKET_SIZE - 1);
+ assert((entry->flags & XEN_MAPCACHE_ENTRY_GRANT) == 0);
+
+ address_index = new_phys_addr >> mc->bucket_shift;
+ address_offset = new_phys_addr & (mc->bucket_size - 1);
trace_xen_replace_cache_entry_dummy(old_phys_addr, new_phys_addr);
xen_remap_bucket(mc, entry, entry->vaddr_base,
- cache_size, address_index, false);
+ cache_size, address_index, false,
+ false, false, old_phys_addr);
if (!test_bits(address_offset >> XC_PAGE_SHIFT,
test_bit_size >> XC_PAGE_SHIFT,
entry->valid_mapping)) {
diff --git a/include/block/aio.h b/include/block/aio.h
index 8378553..4ee8193 100644
--- a/include/block/aio.h
+++ b/include/block/aio.h
@@ -629,6 +629,9 @@
*
* Move the currently running coroutine to new_ctx. If the coroutine is already
* running in new_ctx, do nothing.
+ *
+ * Note that this function cannot reschedule from iohandler_ctx to
+ * qemu_aio_context.
*/
void coroutine_fn aio_co_reschedule_self(AioContext *new_ctx);
@@ -661,6 +664,9 @@
* If called from an IOThread this will be the IOThread's AioContext. If
* called from the main thread or with the "big QEMU lock" taken it
* will be the main loop AioContext.
+ *
+ * Note that the return value is never the main loop's iohandler_ctx and the
+ * return value is the main loop AioContext instead.
*/
AioContext *qemu_get_current_aio_context(void);
diff --git a/include/block/raw-aio.h b/include/block/raw-aio.h
index 20e000b..6267068 100644
--- a/include/block/raw-aio.h
+++ b/include/block/raw-aio.h
@@ -60,6 +60,7 @@
int coroutine_fn laio_co_submit(int fd, uint64_t offset, QEMUIOVector *qiov,
int type, uint64_t dev_max_batch);
+bool laio_has_fdsync(int);
void laio_detach_aio_context(LinuxAioState *s, AioContext *old_context);
void laio_attach_aio_context(LinuxAioState *s, AioContext *new_context);
#endif
diff --git a/include/crypto/block.h b/include/crypto/block.h
index 92e823c..5b5d039 100644
--- a/include/crypto/block.h
+++ b/include/crypto/block.h
@@ -76,7 +76,6 @@
* @readfunc: callback for reading data from the volume
* @opaque: data to pass to @readfunc
* @flags: bitmask of QCryptoBlockOpenFlags values
- * @n_threads: allow concurrent I/O from up to @n_threads threads
* @errp: pointer to a NULL-initialized error object
*
* Create a new block encryption object for an existing
@@ -113,7 +112,6 @@
QCryptoBlockReadFunc readfunc,
void *opaque,
unsigned int flags,
- size_t n_threads,
Error **errp);
typedef enum {
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index c60fac9..849ba37 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -15,6 +15,7 @@
#include "hw/cpu/a15mpcore.h"
#include "hw/arm/armv7m.h"
#include "hw/intc/aspeed_vic.h"
+#include "hw/intc/aspeed_intc.h"
#include "hw/misc/aspeed_scu.h"
#include "hw/adc/aspeed_adc.h"
#include "hw/misc/aspeed_sdmc.h"
@@ -26,6 +27,7 @@
#include "hw/ssi/aspeed_smc.h"
#include "hw/misc/aspeed_hace.h"
#include "hw/misc/aspeed_sbc.h"
+#include "hw/misc/aspeed_sli.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
@@ -38,11 +40,12 @@
#include "hw/misc/aspeed_peci.h"
#include "hw/fsi/aspeed_apb2opb.h"
#include "hw/char/serial.h"
+#include "hw/intc/arm_gicv3.h"
#define ASPEED_SPIS_NUM 2
#define ASPEED_EHCIS_NUM 2
-#define ASPEED_WDTS_NUM 4
-#define ASPEED_CPUS_NUM 2
+#define ASPEED_WDTS_NUM 8
+#define ASPEED_CPUS_NUM 4
#define ASPEED_MACS_NUM 4
#define ASPEED_UARTS_NUM 13
#define ASPEED_JTAG_NUM 2
@@ -56,11 +59,13 @@
MemoryRegion sram;
MemoryRegion spi_boot_container;
MemoryRegion spi_boot;
+ AddressSpace dram_as;
AspeedRtcState rtc;
AspeedTimerCtrlState timerctrl;
AspeedI2CState i2c;
AspeedI3CState i3c;
AspeedSCUState scu;
+ AspeedSCUState scuio;
AspeedHACEState hace;
AspeedXDMAState xdma;
AspeedADCState adc;
@@ -68,6 +73,8 @@
AspeedSMCState spi[ASPEED_SPIS_NUM];
EHCISysBusState ehci[ASPEED_EHCIS_NUM];
AspeedSBCState sbc;
+ AspeedSLIState sli;
+ AspeedSLIState sliio;
MemoryRegion secsram;
UnimplementedDeviceState sbc_unimplemented;
AspeedSDMCState sdmc;
@@ -117,6 +124,18 @@
#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+struct Aspeed27x0SoCState {
+ AspeedSoCState parent;
+
+ ARMCPU cpu[ASPEED_CPUS_NUM];
+ AspeedINTCState intc;
+ GICv3State gic;
+ MemoryRegion dram_empty;
+};
+
+#define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
+
struct Aspeed10x0SoCState {
AspeedSoCState parent;
@@ -168,11 +187,13 @@
ASPEED_DEV_UART13,
ASPEED_DEV_VUART,
ASPEED_DEV_FMC,
+ ASPEED_DEV_SPI0,
ASPEED_DEV_SPI1,
ASPEED_DEV_SPI2,
ASPEED_DEV_EHCI1,
ASPEED_DEV_EHCI2,
ASPEED_DEV_VIC,
+ ASPEED_DEV_INTC,
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
@@ -222,6 +243,11 @@
ASPEED_DEV_JTAG1,
ASPEED_DEV_FSI1,
ASPEED_DEV_FSI2,
+ ASPEED_DEV_SCUIO,
+ ASPEED_DEV_SLI,
+ ASPEED_DEV_SLIIO,
+ ASPEED_GIC_DIST,
+ ASPEED_GIC_REDIST,
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
new file mode 100644
index 0000000..18cb434
--- /dev/null
+++ b/include/hw/intc/aspeed_intc.h
@@ -0,0 +1,44 @@
+/*
+ * ASPEED INTC Controller
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_INTC_H
+#define ASPEED_INTC_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+#include "hw/or-irq.h"
+
+#define TYPE_ASPEED_INTC "aspeed.intc"
+#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
+OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
+
+#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
+#define ASPEED_INTC_NR_INTS 9
+
+struct AspeedINTCState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t regs[ASPEED_INTC_NR_REGS];
+ OrIRQState orgates[ASPEED_INTC_NR_INTS];
+ qemu_irq output_pins[ASPEED_INTC_NR_INTS];
+
+ uint32_t enable[ASPEED_INTC_NR_INTS];
+ uint32_t mask[ASPEED_INTC_NR_INTS];
+ uint32_t pending[ASPEED_INTC_NR_INTS];
+};
+
+struct AspeedINTCClass {
+ SysBusDeviceClass parent_class;
+
+ uint32_t num_lines;
+ uint32_t num_ints;
+};
+
+#endif /* ASPEED_INTC_H */
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 7cb6018..58db28d 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -19,10 +19,13 @@
#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
+#define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
+#define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
#define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
+#define ASPEED_AST2700_SCU_NR_REGS (0xE20 >> 2)
struct AspeedSCUState {
/*< private >*/
@@ -31,7 +34,7 @@
/*< public >*/
MemoryRegion iomem;
- uint32_t regs[ASPEED_AST2600_SCU_NR_REGS];
+ uint32_t regs[ASPEED_AST2700_SCU_NR_REGS];
uint32_t silicon_rev;
uint32_t hw_strap1;
uint32_t hw_strap2;
@@ -48,6 +51,9 @@
#define AST2600_A3_SILICON_REV 0x05030303U
#define AST1030_A0_SILICON_REV 0x80000000U
#define AST1030_A1_SILICON_REV 0x80010000U
+#define AST2700_A0_SILICON_REV 0x06000103U
+#define AST2720_A0_SILICON_REV 0x06000203U
+#define AST2750_A0_SILICON_REV 0x06000003U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
@@ -87,7 +93,8 @@
* 1. 2012/12/29 Ryan Chen Create
*/
-/* SCU08 Clock Selection Register
+/*
+ * SCU08 Clock Selection Register
*
* 31 Enable Video Engine clock dynamic slow down
* 30:28 Video Engine clock slow down setting
@@ -109,7 +116,8 @@
*/
#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
-/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
+/*
+ * SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
*
* 18 H-PLL parameter selection
* 0: Select H-PLL by strapping resistors
@@ -127,7 +135,8 @@
#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
#define SCU_AST2400_H_PLL_OFF (0x1 << 16)
-/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
+/*
+ * SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
*
* 21 Enable H-PLL reset
* 20 Enable H-PLL bypass mode
@@ -144,7 +153,8 @@
#define SCU_H_PLL_BYPASS_EN (0x1 << 20)
#define SCU_H_PLL_OFF (0x1 << 19)
-/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)
+/*
+ * SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)
*
* 31:29 Software defined strapping registers
* 28:27 DRAM size setting (for VGA driver use)
@@ -361,4 +371,31 @@
*/
#define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf)
+/*
+ * SCU280 Clock Selection 1 Register (for Aspeed AST2700 SCUIO)
+ *
+ * 31:29 MHCLK_DIV
+ * 28 Reserved
+ * 27:25 RGMIICLK_DIV
+ * 24 Reserved
+ * 23:21 RMIICLK_DIV
+ * 20:18 PCLK_DIV
+ * 17:14 SDCLK_DIV
+ * 13 SDCLK_SEL
+ * 12 UART13CLK_SEL
+ * 11 UART12CLK_SEL
+ * 10 UART11CLK_SEL
+ * 9 UART10CLK_SEL
+ * 8 UART9CLK_SEL
+ * 7 UART8CLK_SEL
+ * 6 UART7CLK_SEL
+ * 5 UART6CLK_SEL
+ * 4 UARTDBCLK_SEL
+ * 3 UART4CLK_SEL
+ * 2 UART3CLK_SEL
+ * 1 UART2CLK_SEL
+ * 0 UART1CLK_SEL
+ */
+#define SCUIO_AST2700_CLK_GET_PCLK_DIV(x) (((x) >> 18) & 0x7)
+
#endif /* ASPEED_SCU_H */
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
index ec2d59a..61c9795 100644
--- a/include/hw/misc/aspeed_sdmc.h
+++ b/include/hw/misc/aspeed_sdmc.h
@@ -17,6 +17,7 @@
#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
+#define TYPE_ASPEED_2700_SDMC TYPE_ASPEED_SDMC "-ast2700"
/*
* SDMC has 174 documented registers. In addition the u-boot device tree
@@ -29,7 +30,7 @@
* time, and the other is in the DDR-PHY IP which is used during DDR-PHY
* training.
*/
-#define ASPEED_SDMC_NR_REGS (0x500 >> 2)
+#define ASPEED_SDMC_NR_REGS (0x1000 >> 2)
struct AspeedSDMCState {
/*< private >*/
@@ -41,6 +42,7 @@
uint32_t regs[ASPEED_SDMC_NR_REGS];
uint64_t ram_size;
uint64_t max_ram_size;
+ bool unlocked;
};
@@ -51,6 +53,7 @@
const uint64_t *valid_ram_sizes;
uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
+ bool is_bus64bit;
};
#endif /* ASPEED_SDMC_H */
diff --git a/include/hw/misc/aspeed_sli.h b/include/hw/misc/aspeed_sli.h
new file mode 100644
index 0000000..23f346a
--- /dev/null
+++ b/include/hw/misc/aspeed_sli.h
@@ -0,0 +1,27 @@
+/*
+ * ASPEED SLI Controller
+ *
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_SLI_H
+#define ASPEED_SLI_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_SLI "aspeed.sli"
+#define TYPE_ASPEED_2700_SLI TYPE_ASPEED_SLI "-ast2700"
+#define TYPE_ASPEED_2700_SLIIO TYPE_ASPEED_SLI "io" "-ast2700"
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedSLIState, ASPEED_SLI)
+
+#define ASPEED_SLI_NR_REGS (0x500 >> 2)
+
+struct AspeedSLIState {
+ SysBusDevice parent;
+ MemoryRegion iomem;
+
+ uint32_t regs[ASPEED_SLI_NR_REGS];
+};
+
+#endif /* ASPEED_SLI_H */
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index 8e1dda5..234dca3 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -76,6 +76,7 @@
AddressSpace flash_as;
MemoryRegion *dram_mr;
AddressSpace dram_as;
+ uint64_t dram_base;
AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX];
@@ -106,6 +107,7 @@
uint32_t features;
hwaddr dma_flash_mask;
hwaddr dma_dram_mask;
+ uint32_t dma_start_length;
uint32_t nregs;
uint32_t (*segment_to_reg)(const AspeedSMCState *s,
const AspeedSegments *seg);
@@ -113,6 +115,7 @@
AspeedSegments *seg);
void (*dma_ctrl)(AspeedSMCState *s, uint32_t value);
int (*addr_width)(const AspeedSMCState *s);
+ const MemoryRegionOps *reg_ops;
};
#endif /* ASPEED_SMC_H */
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index e90ef86..830b0a7 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -19,9 +19,10 @@
#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
+#define TYPE_ASPEED_2700_WDT TYPE_ASPEED_WDT "-ast2700"
#define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
-#define ASPEED_WDT_REGS_MAX (0x30 / 4)
+#define ASPEED_WDT_REGS_MAX (0x80 / 4)
struct AspeedWDTState {
/*< private >*/
diff --git a/include/hw/xen/xen-hvm-common.h b/include/hw/xen/xen-hvm-common.h
index 65a51aa..3d79623 100644
--- a/include/hw/xen/xen-hvm-common.h
+++ b/include/hw/xen/xen-hvm-common.h
@@ -16,6 +16,7 @@
#include <xen/hvm/ioreq.h>
extern MemoryRegion xen_memory;
+extern MemoryRegion xen_grants;
extern MemoryListener xen_io_listener;
extern DeviceListener xen_device_listener;
@@ -29,6 +30,8 @@
do { } while (0)
#endif
+#define XEN_GRANT_ADDR_OFF (1ULL << 63)
+
static inline uint32_t xen_vcpu_eport(shared_iopage_t *shared_page, int i)
{
return shared_page->vcpu_ioreq[i].vp_eport;
diff --git a/include/sysemu/xen-mapcache.h b/include/sysemu/xen-mapcache.h
index 1ec9e66..b5e3ea1 100644
--- a/include/sysemu/xen-mapcache.h
+++ b/include/sysemu/xen-mapcache.h
@@ -19,6 +19,7 @@
void xen_map_cache_init(phys_offset_to_gaddr_t f,
void *opaque);
uint8_t *xen_map_cache(MemoryRegion *mr, hwaddr phys_addr, hwaddr size,
+ ram_addr_t ram_addr_offset,
uint8_t lock, bool dma,
bool is_write);
ram_addr_t xen_ram_addr_from_mapcache(void *ptr);
@@ -37,6 +38,7 @@
static inline uint8_t *xen_map_cache(MemoryRegion *mr,
hwaddr phys_addr,
hwaddr size,
+ ram_addr_t ram_addr_offset,
uint8_t lock,
bool dma,
bool is_write)
diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h
index 3445888..d70eacf 100644
--- a/include/sysemu/xen.h
+++ b/include/sysemu/xen.h
@@ -50,4 +50,5 @@
#endif /* CONFIG_XEN_IS_POSSIBLE */
bool xen_mr_is_memory(MemoryRegion *mr);
+bool xen_mr_is_grants(MemoryRegion *mr);
#endif
diff --git a/meson.build b/meson.build
index ec59eff..97e00d6 100644
--- a/meson.build
+++ b/meson.build
@@ -1201,6 +1201,24 @@
required: get_option('zstd'),
method: 'pkg-config')
endif
+qpl = not_found
+if not get_option('qpl').auto() or have_system
+ qpl = dependency('qpl', version: '>=1.5.0',
+ required: get_option('qpl'),
+ method: 'pkg-config')
+endif
+uadk = not_found
+if not get_option('uadk').auto() or have_system
+ libwd = dependency('libwd', version: '>=2.6',
+ required: get_option('uadk'),
+ method: 'pkg-config')
+ libwd_comp = dependency('libwd_comp', version: '>=2.6',
+ required: get_option('uadk'),
+ method: 'pkg-config')
+ if libwd.found() and libwd_comp.found()
+ uadk = declare_dependency(dependencies: [libwd, libwd_comp])
+ endif
+endif
virgl = not_found
have_vhost_user_gpu = have_tools and host_os == 'linux' and pixman.found()
@@ -1885,11 +1903,9 @@
rdma = not_found
if not get_option('rdma').auto() or have_system
- libumad = cc.find_library('ibumad', required: get_option('rdma'))
rdma_libs = [cc.find_library('rdmacm', has_headers: ['rdma/rdma_cma.h'],
required: get_option('rdma')),
- cc.find_library('ibverbs', required: get_option('rdma')),
- libumad]
+ cc.find_library('ibverbs', required: get_option('rdma'))]
rdma = declare_dependency(dependencies: rdma_libs)
foreach lib: rdma_libs
if not lib.found()
@@ -2335,6 +2351,8 @@
config_host_data.set('CONFIG_STATX', has_statx)
config_host_data.set('CONFIG_STATX_MNT_ID', has_statx_mnt_id)
config_host_data.set('CONFIG_ZSTD', zstd.found())
+config_host_data.set('CONFIG_QPL', qpl.found())
+config_host_data.set('CONFIG_UADK', uadk.found())
config_host_data.set('CONFIG_FUSE', fuse.found())
config_host_data.set('CONFIG_FUSE_LSEEK', fuse_lseek.found())
config_host_data.set('CONFIG_SPICE_PROTOCOL', spice_protocol.found())
@@ -3232,7 +3250,6 @@
'scripts/tracetool/format/log_stap.py',
'scripts/tracetool/format/stap.py',
'scripts/tracetool/__init__.py',
- 'scripts/tracetool/vcpu.py'
)
qemu_version_cmd = [find_program('scripts/qemu-version.sh'),
@@ -4449,6 +4466,8 @@
summary_info += {'bzip2 support': libbzip2}
summary_info += {'lzfse support': liblzfse}
summary_info += {'zstd support': zstd}
+summary_info += {'Query Processing Library support': qpl}
+summary_info += {'UADK Library support': uadk}
summary_info += {'NUMA host support': numa}
summary_info += {'capstone': capstone}
summary_info += {'libpmem support': libpmem}
diff --git a/meson_options.txt b/meson_options.txt
index 4c1583e..7a79dd8 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -259,6 +259,10 @@
description: 'xkbcommon support')
option('zstd', type : 'feature', value : 'auto',
description: 'zstd compression support')
+option('qpl', type : 'feature', value : 'auto',
+ description: 'Query Processing Library support')
+option('uadk', type : 'feature', value : 'auto',
+ description: 'UADK Library support')
option('fuse', type: 'feature', value: 'auto',
description: 'FUSE block device export')
option('fuse_lseek', type : 'feature', value : 'auto',
diff --git a/migration/meson.build b/migration/meson.build
index bdc3244..5ce2acb4 100644
--- a/migration/meson.build
+++ b/migration/meson.build
@@ -39,6 +39,8 @@
system_ss.add(when: rdma, if_true: files('rdma.c'))
system_ss.add(when: zstd, if_true: files('multifd-zstd.c'))
+system_ss.add(when: qpl, if_true: files('multifd-qpl.c'))
+system_ss.add(when: uadk, if_true: files('multifd-uadk.c'))
specific_ss.add(when: 'CONFIG_SYSTEM_ONLY',
if_true: files('ram.c',
diff --git a/migration/multifd-qpl.c b/migration/multifd-qpl.c
new file mode 100644
index 0000000..9265098
--- /dev/null
+++ b/migration/multifd-qpl.c
@@ -0,0 +1,762 @@
+/*
+ * Multifd qpl compression accelerator implementation
+ *
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * Authors:
+ * Yuan Liu<yuan1.liu@intel.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "qapi/qapi-types-migration.h"
+#include "exec/ramblock.h"
+#include "multifd.h"
+#include "qpl/qpl.h"
+
+/* Maximum number of retries to resubmit a job if IAA work queues are full */
+#define MAX_SUBMIT_RETRY_NUM (3)
+
+typedef struct {
+ /* the QPL hardware path job */
+ qpl_job *job;
+ /* indicates if fallback to software path is required */
+ bool fallback_sw_path;
+ /* output data from the software path */
+ uint8_t *sw_output;
+ /* output data length from the software path */
+ uint32_t sw_output_len;
+} QplHwJob;
+
+typedef struct {
+ /* array of hardware jobs, the number of jobs equals the number pages */
+ QplHwJob *hw_jobs;
+ /* the QPL software job for the slow path and software fallback */
+ qpl_job *sw_job;
+ /* the number of pages that the QPL needs to process at one time */
+ uint32_t page_num;
+ /* array of compressed page buffers */
+ uint8_t *zbuf;
+ /* array of compressed page lengths */
+ uint32_t *zlen;
+ /* the status of the hardware device */
+ bool hw_avail;
+} QplData;
+
+/**
+ * check_hw_avail: check if IAA hardware is available
+ *
+ * If the IAA hardware does not exist or is unavailable,
+ * the QPL hardware job initialization will fail.
+ *
+ * Returns true if IAA hardware is available, otherwise false.
+ *
+ * @job_size: indicates the hardware job size if hardware is available
+ */
+static bool check_hw_avail(uint32_t *job_size)
+{
+ qpl_path_t path = qpl_path_hardware;
+ uint32_t size = 0;
+ qpl_job *job;
+
+ if (qpl_get_job_size(path, &size) != QPL_STS_OK) {
+ return false;
+ }
+ assert(size > 0);
+ job = g_malloc0(size);
+ if (qpl_init_job(path, job) != QPL_STS_OK) {
+ g_free(job);
+ return false;
+ }
+ g_free(job);
+ *job_size = size;
+ return true;
+}
+
+/**
+ * multifd_qpl_free_sw_job: clean up software job
+ *
+ * Free the software job resources.
+ *
+ * @qpl: pointer to the QplData structure
+ */
+static void multifd_qpl_free_sw_job(QplData *qpl)
+{
+ assert(qpl);
+ if (qpl->sw_job) {
+ qpl_fini_job(qpl->sw_job);
+ g_free(qpl->sw_job);
+ qpl->sw_job = NULL;
+ }
+}
+
+/**
+ * multifd_qpl_free_jobs: clean up hardware jobs
+ *
+ * Free all hardware job resources.
+ *
+ * @qpl: pointer to the QplData structure
+ */
+static void multifd_qpl_free_hw_job(QplData *qpl)
+{
+ assert(qpl);
+ if (qpl->hw_jobs) {
+ for (int i = 0; i < qpl->page_num; i++) {
+ qpl_fini_job(qpl->hw_jobs[i].job);
+ g_free(qpl->hw_jobs[i].job);
+ qpl->hw_jobs[i].job = NULL;
+ }
+ g_free(qpl->hw_jobs);
+ qpl->hw_jobs = NULL;
+ }
+}
+
+/**
+ * multifd_qpl_init_sw_job: initialize a software job
+ *
+ * Use the QPL software path to initialize a job
+ *
+ * @qpl: pointer to the QplData structure
+ * @errp: pointer to an error
+ */
+static int multifd_qpl_init_sw_job(QplData *qpl, Error **errp)
+{
+ qpl_path_t path = qpl_path_software;
+ uint32_t size = 0;
+ qpl_job *job = NULL;
+ qpl_status status;
+
+ status = qpl_get_job_size(path, &size);
+ if (status != QPL_STS_OK) {
+ error_setg(errp, "qpl_get_job_size failed with error %d", status);
+ return -1;
+ }
+ job = g_malloc0(size);
+ status = qpl_init_job(path, job);
+ if (status != QPL_STS_OK) {
+ error_setg(errp, "qpl_init_job failed with error %d", status);
+ g_free(job);
+ return -1;
+ }
+ qpl->sw_job = job;
+ return 0;
+}
+
+/**
+ * multifd_qpl_init_jobs: initialize hardware jobs
+ *
+ * Use the QPL hardware path to initialize jobs
+ *
+ * @qpl: pointer to the QplData structure
+ * @size: the size of QPL hardware path job
+ * @errp: pointer to an error
+ */
+static void multifd_qpl_init_hw_job(QplData *qpl, uint32_t size, Error **errp)
+{
+ qpl_path_t path = qpl_path_hardware;
+ qpl_job *job = NULL;
+ qpl_status status;
+
+ qpl->hw_jobs = g_new0(QplHwJob, qpl->page_num);
+ for (int i = 0; i < qpl->page_num; i++) {
+ job = g_malloc0(size);
+ status = qpl_init_job(path, job);
+ /* the job initialization should succeed after check_hw_avail */
+ assert(status == QPL_STS_OK);
+ qpl->hw_jobs[i].job = job;
+ }
+}
+
+/**
+ * multifd_qpl_init: initialize QplData structure
+ *
+ * Allocate and initialize a QplData structure
+ *
+ * Returns a QplData pointer on success or NULL on error
+ *
+ * @num: the number of pages
+ * @size: the page size
+ * @errp: pointer to an error
+ */
+static QplData *multifd_qpl_init(uint32_t num, uint32_t size, Error **errp)
+{
+ uint32_t job_size = 0;
+ QplData *qpl;
+
+ qpl = g_new0(QplData, 1);
+ qpl->page_num = num;
+ if (multifd_qpl_init_sw_job(qpl, errp) != 0) {
+ g_free(qpl);
+ return NULL;
+ }
+ qpl->hw_avail = check_hw_avail(&job_size);
+ if (qpl->hw_avail) {
+ multifd_qpl_init_hw_job(qpl, job_size, errp);
+ }
+ qpl->zbuf = g_malloc0(size * num);
+ qpl->zlen = g_new0(uint32_t, num);
+ return qpl;
+}
+
+/**
+ * multifd_qpl_deinit: clean up QplData structure
+ *
+ * Free jobs, buffers and the QplData structure
+ *
+ * @qpl: pointer to the QplData structure
+ */
+static void multifd_qpl_deinit(QplData *qpl)
+{
+ if (qpl) {
+ multifd_qpl_free_sw_job(qpl);
+ multifd_qpl_free_hw_job(qpl);
+ g_free(qpl->zbuf);
+ g_free(qpl->zlen);
+ g_free(qpl);
+ }
+}
+
+/**
+ * multifd_qpl_send_setup: set up send side
+ *
+ * Set up the channel with QPL compression.
+ *
+ * Returns 0 on success or -1 on error
+ *
+ * @p: Params for the channel being used
+ * @errp: pointer to an error
+ */
+static int multifd_qpl_send_setup(MultiFDSendParams *p, Error **errp)
+{
+ QplData *qpl;
+
+ qpl = multifd_qpl_init(p->page_count, p->page_size, errp);
+ if (!qpl) {
+ return -1;
+ }
+ p->compress_data = qpl;
+
+ /*
+ * the page will be compressed independently and sent using an IOV. The
+ * additional two IOVs are used to store packet header and compressed data
+ * length
+ */
+ p->iov = g_new0(struct iovec, p->page_count + 2);
+ return 0;
+}
+
+/**
+ * multifd_qpl_send_cleanup: clean up send side
+ *
+ * Close the channel and free memory.
+ *
+ * @p: Params for the channel being used
+ * @errp: pointer to an error
+ */
+static void multifd_qpl_send_cleanup(MultiFDSendParams *p, Error **errp)
+{
+ multifd_qpl_deinit(p->compress_data);
+ p->compress_data = NULL;
+ g_free(p->iov);
+ p->iov = NULL;
+}
+
+/**
+ * multifd_qpl_prepare_job: prepare the job
+ *
+ * Set the QPL job parameters and properties.
+ *
+ * @job: pointer to the qpl_job structure
+ * @is_compression: indicates compression and decompression
+ * @input: pointer to the input data buffer
+ * @input_len: the length of the input data
+ * @output: pointer to the output data buffer
+ * @output_len: the length of the output data
+ */
+static void multifd_qpl_prepare_job(qpl_job *job, bool is_compression,
+ uint8_t *input, uint32_t input_len,
+ uint8_t *output, uint32_t output_len)
+{
+ job->op = is_compression ? qpl_op_compress : qpl_op_decompress;
+ job->next_in_ptr = input;
+ job->next_out_ptr = output;
+ job->available_in = input_len;
+ job->available_out = output_len;
+ job->flags = QPL_FLAG_FIRST | QPL_FLAG_LAST | QPL_FLAG_OMIT_VERIFY;
+ /* only supports compression level 1 */
+ job->level = 1;
+}
+
+/**
+ * multifd_qpl_prepare_comp_job: prepare the compression job
+ *
+ * Set the compression job parameters and properties.
+ *
+ * @job: pointer to the qpl_job structure
+ * @input: pointer to the input data buffer
+ * @output: pointer to the output data buffer
+ * @size: the page size
+ */
+static void multifd_qpl_prepare_comp_job(qpl_job *job, uint8_t *input,
+ uint8_t *output, uint32_t size)
+{
+ /*
+ * Set output length to less than the page size to force the job to
+ * fail in case it compresses to a larger size. We'll send that page
+ * without compression and skip the decompression operation on the
+ * destination.
+ */
+ multifd_qpl_prepare_job(job, true, input, size, output, size - 1);
+}
+
+/**
+ * multifd_qpl_prepare_decomp_job: prepare the decompression job
+ *
+ * Set the decompression job parameters and properties.
+ *
+ * @job: pointer to the qpl_job structure
+ * @input: pointer to the input data buffer
+ * @len: the length of the input data
+ * @output: pointer to the output data buffer
+ * @size: the page size
+ */
+static void multifd_qpl_prepare_decomp_job(qpl_job *job, uint8_t *input,
+ uint32_t len, uint8_t *output,
+ uint32_t size)
+{
+ multifd_qpl_prepare_job(job, false, input, len, output, size);
+}
+
+/**
+ * multifd_qpl_fill_iov: fill in the IOV
+ *
+ * Fill in the QPL packet IOV
+ *
+ * @p: Params for the channel being used
+ * @data: pointer to the IOV data
+ * @len: The length of the IOV data
+ */
+static void multifd_qpl_fill_iov(MultiFDSendParams *p, uint8_t *data,
+ uint32_t len)
+{
+ p->iov[p->iovs_num].iov_base = data;
+ p->iov[p->iovs_num].iov_len = len;
+ p->iovs_num++;
+ p->next_packet_size += len;
+}
+
+/**
+ * multifd_qpl_fill_packet: fill the compressed page into the QPL packet
+ *
+ * Fill the compressed page length and IOV into the QPL packet
+ *
+ * @idx: The index of the compressed length array
+ * @p: Params for the channel being used
+ * @data: pointer to the compressed page buffer
+ * @len: The length of the compressed page
+ */
+static void multifd_qpl_fill_packet(uint32_t idx, MultiFDSendParams *p,
+ uint8_t *data, uint32_t len)
+{
+ QplData *qpl = p->compress_data;
+
+ qpl->zlen[idx] = cpu_to_be32(len);
+ multifd_qpl_fill_iov(p, data, len);
+}
+
+/**
+ * multifd_qpl_submit_job: submit a job to the hardware
+ *
+ * Submit a QPL hardware job to the IAA device
+ *
+ * Returns true if the job is submitted successfully, otherwise false.
+ *
+ * @job: pointer to the qpl_job structure
+ */
+static bool multifd_qpl_submit_job(qpl_job *job)
+{
+ qpl_status status;
+ uint32_t num = 0;
+
+retry:
+ status = qpl_submit_job(job);
+ if (status == QPL_STS_QUEUES_ARE_BUSY_ERR) {
+ if (num < MAX_SUBMIT_RETRY_NUM) {
+ num++;
+ goto retry;
+ }
+ }
+ return (status == QPL_STS_OK);
+}
+
+/**
+ * multifd_qpl_compress_pages_slow_path: compress pages using slow path
+ *
+ * Compress the pages using software. If compression fails, the uncompressed
+ * page will be sent.
+ *
+ * @p: Params for the channel being used
+ */
+static void multifd_qpl_compress_pages_slow_path(MultiFDSendParams *p)
+{
+ QplData *qpl = p->compress_data;
+ uint32_t size = p->page_size;
+ qpl_job *job = qpl->sw_job;
+ uint8_t *zbuf = qpl->zbuf;
+ uint8_t *buf;
+
+ for (int i = 0; i < p->pages->normal_num; i++) {
+ buf = p->pages->block->host + p->pages->offset[i];
+ multifd_qpl_prepare_comp_job(job, buf, zbuf, size);
+ if (qpl_execute_job(job) == QPL_STS_OK) {
+ multifd_qpl_fill_packet(i, p, zbuf, job->total_out);
+ } else {
+ /* send the uncompressed page */
+ multifd_qpl_fill_packet(i, p, buf, size);
+ }
+ zbuf += size;
+ }
+}
+
+/**
+ * multifd_qpl_compress_pages: compress pages
+ *
+ * Submit the pages to the IAA hardware for compression. If hardware
+ * compression fails, it falls back to software compression. If software
+ * compression also fails, the uncompressed page is sent.
+ *
+ * @p: Params for the channel being used
+ */
+static void multifd_qpl_compress_pages(MultiFDSendParams *p)
+{
+ QplData *qpl = p->compress_data;
+ MultiFDPages_t *pages = p->pages;
+ uint32_t size = p->page_size;
+ QplHwJob *hw_job;
+ uint8_t *buf;
+ uint8_t *zbuf;
+
+ for (int i = 0; i < pages->normal_num; i++) {
+ buf = pages->block->host + pages->offset[i];
+ zbuf = qpl->zbuf + (size * i);
+ hw_job = &qpl->hw_jobs[i];
+ multifd_qpl_prepare_comp_job(hw_job->job, buf, zbuf, size);
+ if (multifd_qpl_submit_job(hw_job->job)) {
+ hw_job->fallback_sw_path = false;
+ } else {
+ /*
+ * The IAA work queue is full, any immediate subsequent job
+ * submission is likely to fail, sending the page via the QPL
+ * software path at this point gives us a better chance of
+ * finding the queue open for the next pages.
+ */
+ hw_job->fallback_sw_path = true;
+ multifd_qpl_prepare_comp_job(qpl->sw_job, buf, zbuf, size);
+ if (qpl_execute_job(qpl->sw_job) == QPL_STS_OK) {
+ hw_job->sw_output = zbuf;
+ hw_job->sw_output_len = qpl->sw_job->total_out;
+ } else {
+ hw_job->sw_output = buf;
+ hw_job->sw_output_len = size;
+ }
+ }
+ }
+
+ for (int i = 0; i < pages->normal_num; i++) {
+ buf = pages->block->host + pages->offset[i];
+ zbuf = qpl->zbuf + (size * i);
+ hw_job = &qpl->hw_jobs[i];
+ if (hw_job->fallback_sw_path) {
+ multifd_qpl_fill_packet(i, p, hw_job->sw_output,
+ hw_job->sw_output_len);
+ continue;
+ }
+ if (qpl_wait_job(hw_job->job) == QPL_STS_OK) {
+ multifd_qpl_fill_packet(i, p, zbuf, hw_job->job->total_out);
+ } else {
+ /* send the uncompressed page */
+ multifd_qpl_fill_packet(i, p, buf, size);
+ }
+ }
+}
+
+/**
+ * multifd_qpl_send_prepare: prepare data to be able to send
+ *
+ * Create a compressed buffer with all the pages that we are going to
+ * send.
+ *
+ * Returns 0 on success or -1 on error
+ *
+ * @p: Params for the channel being used
+ * @errp: pointer to an error
+ */
+static int multifd_qpl_send_prepare(MultiFDSendParams *p, Error **errp)
+{
+ QplData *qpl = p->compress_data;
+ uint32_t len = 0;
+
+ if (!multifd_send_prepare_common(p)) {
+ goto out;
+ }
+
+ /* The first IOV is used to store the compressed page lengths */
+ len = p->pages->normal_num * sizeof(uint32_t);
+ multifd_qpl_fill_iov(p, (uint8_t *) qpl->zlen, len);
+ if (qpl->hw_avail) {
+ multifd_qpl_compress_pages(p);
+ } else {
+ multifd_qpl_compress_pages_slow_path(p);
+ }
+
+out:
+ p->flags |= MULTIFD_FLAG_QPL;
+ multifd_send_fill_packet(p);
+ return 0;
+}
+
+/**
+ * multifd_qpl_recv_setup: set up receive side
+ *
+ * Create the compressed channel and buffer.
+ *
+ * Returns 0 on success or -1 on error
+ *
+ * @p: Params for the channel being used
+ * @errp: pointer to an error
+ */
+static int multifd_qpl_recv_setup(MultiFDRecvParams *p, Error **errp)
+{
+ QplData *qpl;
+
+ qpl = multifd_qpl_init(p->page_count, p->page_size, errp);
+ if (!qpl) {
+ return -1;
+ }
+ p->compress_data = qpl;
+ return 0;
+}
+
+/**
+ * multifd_qpl_recv_cleanup: set up receive side
+ *
+ * Close the channel and free memory.
+ *
+ * @p: Params for the channel being used
+ */
+static void multifd_qpl_recv_cleanup(MultiFDRecvParams *p)
+{
+ multifd_qpl_deinit(p->compress_data);
+ p->compress_data = NULL;
+}
+
+/**
+ * multifd_qpl_process_and_check_job: process and check a QPL job
+ *
+ * Process the job and check whether the job output length is the
+ * same as the specified length
+ *
+ * Returns true if the job execution succeeded and the output length
+ * is equal to the specified length, otherwise false.
+ *
+ * @job: pointer to the qpl_job structure
+ * @is_hardware: indicates whether the job is a hardware job
+ * @len: Specified output length
+ * @errp: pointer to an error
+ */
+static bool multifd_qpl_process_and_check_job(qpl_job *job, bool is_hardware,
+ uint32_t len, Error **errp)
+{
+ qpl_status status;
+
+ status = (is_hardware ? qpl_wait_job(job) : qpl_execute_job(job));
+ if (status != QPL_STS_OK) {
+ error_setg(errp, "qpl job failed with error %d", status);
+ return false;
+ }
+ if (job->total_out != len) {
+ error_setg(errp, "qpl decompressed len %u, expected len %u",
+ job->total_out, len);
+ return false;
+ }
+ return true;
+}
+
+/**
+ * multifd_qpl_decompress_pages_slow_path: decompress pages using slow path
+ *
+ * Decompress the pages using software
+ *
+ * Returns 0 on success or -1 on error
+ *
+ * @p: Params for the channel being used
+ * @errp: pointer to an error
+ */
+static int multifd_qpl_decompress_pages_slow_path(MultiFDRecvParams *p,
+ Error **errp)
+{
+ QplData *qpl = p->compress_data;
+ uint32_t size = p->page_size;
+ qpl_job *job = qpl->sw_job;
+ uint8_t *zbuf = qpl->zbuf;
+ uint8_t *addr;
+ uint32_t len;
+
+ for (int i = 0; i < p->normal_num; i++) {
+ len = qpl->zlen[i];
+ addr = p->host + p->normal[i];
+ /* the page is uncompressed, load it */
+ if (len == size) {
+ memcpy(addr, zbuf, size);
+ zbuf += size;
+ continue;
+ }
+ multifd_qpl_prepare_decomp_job(job, zbuf, len, addr, size);
+ if (!multifd_qpl_process_and_check_job(job, false, size, errp)) {
+ return -1;
+ }
+ zbuf += len;
+ }
+ return 0;
+}
+
+/**
+ * multifd_qpl_decompress_pages: decompress pages
+ *
+ * Decompress the pages using the IAA hardware. If hardware
+ * decompression fails, it falls back to software decompression.
+ *
+ * Returns 0 on success or -1 on error
+ *
+ * @p: Params for the channel being used
+ * @errp: pointer to an error
+ */
+static int multifd_qpl_decompress_pages(MultiFDRecvParams *p, Error **errp)
+{
+ QplData *qpl = p->compress_data;
+ uint32_t size = p->page_size;
+ uint8_t *zbuf = qpl->zbuf;
+ uint8_t *addr;
+ uint32_t len;
+ qpl_job *job;
+
+ for (int i = 0; i < p->normal_num; i++) {
+ addr = p->host + p->normal[i];
+ len = qpl->zlen[i];
+ /* the page is uncompressed if received length equals the page size */
+ if (len == size) {
+ memcpy(addr, zbuf, size);
+ zbuf += size;
+ continue;
+ }
+
+ job = qpl->hw_jobs[i].job;
+ multifd_qpl_prepare_decomp_job(job, zbuf, len, addr, size);
+ if (multifd_qpl_submit_job(job)) {
+ qpl->hw_jobs[i].fallback_sw_path = false;
+ } else {
+ /*
+ * The IAA work queue is full, any immediate subsequent job
+ * submission is likely to fail, sending the page via the QPL
+ * software path at this point gives us a better chance of
+ * finding the queue open for the next pages.
+ */
+ qpl->hw_jobs[i].fallback_sw_path = true;
+ job = qpl->sw_job;
+ multifd_qpl_prepare_decomp_job(job, zbuf, len, addr, size);
+ if (!multifd_qpl_process_and_check_job(job, false, size, errp)) {
+ return -1;
+ }
+ }
+ zbuf += len;
+ }
+
+ for (int i = 0; i < p->normal_num; i++) {
+ /* ignore pages that have already been processed */
+ if (qpl->zlen[i] == size || qpl->hw_jobs[i].fallback_sw_path) {
+ continue;
+ }
+
+ job = qpl->hw_jobs[i].job;
+ if (!multifd_qpl_process_and_check_job(job, true, size, errp)) {
+ return -1;
+ }
+ }
+ return 0;
+}
+/**
+ * multifd_qpl_recv: read the data from the channel into actual pages
+ *
+ * Read the compressed buffer, and uncompress it into the actual
+ * pages.
+ *
+ * Returns 0 on success or -1 on error
+ *
+ * @p: Params for the channel being used
+ * @errp: pointer to an error
+ */
+static int multifd_qpl_recv(MultiFDRecvParams *p, Error **errp)
+{
+ QplData *qpl = p->compress_data;
+ uint32_t in_size = p->next_packet_size;
+ uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK;
+ uint32_t len = 0;
+ uint32_t zbuf_len = 0;
+ int ret;
+
+ if (flags != MULTIFD_FLAG_QPL) {
+ error_setg(errp, "multifd %u: flags received %x flags expected %x",
+ p->id, flags, MULTIFD_FLAG_QPL);
+ return -1;
+ }
+ multifd_recv_zero_page_process(p);
+ if (!p->normal_num) {
+ assert(in_size == 0);
+ return 0;
+ }
+
+ /* read compressed page lengths */
+ len = p->normal_num * sizeof(uint32_t);
+ assert(len < in_size);
+ ret = qio_channel_read_all(p->c, (void *) qpl->zlen, len, errp);
+ if (ret != 0) {
+ return ret;
+ }
+ for (int i = 0; i < p->normal_num; i++) {
+ qpl->zlen[i] = be32_to_cpu(qpl->zlen[i]);
+ assert(qpl->zlen[i] <= p->page_size);
+ zbuf_len += qpl->zlen[i];
+ }
+
+ /* read compressed pages */
+ assert(in_size == len + zbuf_len);
+ ret = qio_channel_read_all(p->c, (void *) qpl->zbuf, zbuf_len, errp);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (qpl->hw_avail) {
+ return multifd_qpl_decompress_pages(p, errp);
+ }
+ return multifd_qpl_decompress_pages_slow_path(p, errp);
+}
+
+static MultiFDMethods multifd_qpl_ops = {
+ .send_setup = multifd_qpl_send_setup,
+ .send_cleanup = multifd_qpl_send_cleanup,
+ .send_prepare = multifd_qpl_send_prepare,
+ .recv_setup = multifd_qpl_recv_setup,
+ .recv_cleanup = multifd_qpl_recv_cleanup,
+ .recv = multifd_qpl_recv,
+};
+
+static void multifd_qpl_register(void)
+{
+ multifd_register_ops(MULTIFD_COMPRESSION_QPL, &multifd_qpl_ops);
+}
+
+migration_init(multifd_qpl_register);
diff --git a/migration/multifd-uadk.c b/migration/multifd-uadk.c
new file mode 100644
index 0000000..d12353f
--- /dev/null
+++ b/migration/multifd-uadk.c
@@ -0,0 +1,369 @@
+/*
+ * Multifd UADK compression accelerator implementation
+ *
+ * Copyright (c) 2024 Huawei Technologies R & D (UK) Ltd
+ *
+ * Authors:
+ * Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "exec/ramblock.h"
+#include "migration.h"
+#include "multifd.h"
+#include "options.h"
+#include "qemu/error-report.h"
+#include "uadk/wd_comp.h"
+#include "uadk/wd_sched.h"
+
+struct wd_data {
+ handle_t handle;
+ uint8_t *buf;
+ uint32_t *buf_hdr;
+};
+
+static bool uadk_hw_init(void)
+{
+ char alg[] = "zlib";
+ int ret;
+
+ ret = wd_comp_init2(alg, SCHED_POLICY_RR, TASK_HW);
+ if (ret && ret != -WD_EEXIST) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+static struct wd_data *multifd_uadk_init_sess(uint32_t count,
+ uint32_t page_size,
+ bool compress, Error **errp)
+{
+ struct wd_comp_sess_setup ss = {0};
+ struct sched_params param = {0};
+ uint32_t size = count * page_size;
+ struct wd_data *wd;
+
+ wd = g_new0(struct wd_data, 1);
+
+ if (uadk_hw_init()) {
+ ss.alg_type = WD_ZLIB;
+ if (compress) {
+ ss.op_type = WD_DIR_COMPRESS;
+ /* Add an additional page for handling output > input */
+ size += page_size;
+ } else {
+ ss.op_type = WD_DIR_DECOMPRESS;
+ }
+ /* We use default level 1 compression and 4K window size */
+ param.type = ss.op_type;
+ ss.sched_param = ¶m;
+
+ wd->handle = wd_comp_alloc_sess(&ss);
+ if (!wd->handle) {
+ error_setg(errp, "multifd: failed wd_comp_alloc_sess");
+ goto out;
+ }
+ } else {
+ /* For CI test use */
+ warn_report_once("UADK hardware not available. Switch to no compression mode");
+ }
+
+ wd->buf = g_try_malloc(size);
+ if (!wd->buf) {
+ error_setg(errp, "multifd: out of mem for uadk buf");
+ goto out_free_sess;
+ }
+ wd->buf_hdr = g_new0(uint32_t, count);
+ return wd;
+
+out_free_sess:
+ if (wd->handle) {
+ wd_comp_free_sess(wd->handle);
+ }
+out:
+ wd_comp_uninit2();
+ g_free(wd);
+ return NULL;
+}
+
+static void multifd_uadk_uninit_sess(struct wd_data *wd)
+{
+ if (wd->handle) {
+ wd_comp_free_sess(wd->handle);
+ }
+ wd_comp_uninit2();
+ g_free(wd->buf);
+ g_free(wd->buf_hdr);
+ g_free(wd);
+}
+
+/**
+ * multifd_uadk_send_setup: setup send side
+ *
+ * Returns 0 for success or -1 for error
+ *
+ * @p: Params for the channel that we are using
+ * @errp: pointer to an error
+ */
+static int multifd_uadk_send_setup(MultiFDSendParams *p, Error **errp)
+{
+ struct wd_data *wd;
+
+ wd = multifd_uadk_init_sess(p->page_count, p->page_size, true, errp);
+ if (!wd) {
+ return -1;
+ }
+
+ p->compress_data = wd;
+ assert(p->iov == NULL);
+ /*
+ * Each page will be compressed independently and sent using an IOV. The
+ * additional two IOVs are used to store packet header and compressed data
+ * length
+ */
+
+ p->iov = g_new0(struct iovec, p->page_count + 2);
+ return 0;
+}
+
+/**
+ * multifd_uadk_send_cleanup: cleanup send side
+ *
+ * Close the channel and return memory.
+ *
+ * @p: Params for the channel that we are using
+ * @errp: pointer to an error
+ */
+static void multifd_uadk_send_cleanup(MultiFDSendParams *p, Error **errp)
+{
+ struct wd_data *wd = p->compress_data;
+
+ multifd_uadk_uninit_sess(wd);
+ p->compress_data = NULL;
+}
+
+static inline void prepare_next_iov(MultiFDSendParams *p, void *base,
+ uint32_t len)
+{
+ p->iov[p->iovs_num].iov_base = (uint8_t *)base;
+ p->iov[p->iovs_num].iov_len = len;
+ p->next_packet_size += len;
+ p->iovs_num++;
+}
+
+/**
+ * multifd_uadk_send_prepare: prepare data to be able to send
+ *
+ * Create a compressed buffer with all the pages that we are going to
+ * send.
+ *
+ * Returns 0 for success or -1 for error
+ *
+ * @p: Params for the channel that we are using
+ * @errp: pointer to an error
+ */
+static int multifd_uadk_send_prepare(MultiFDSendParams *p, Error **errp)
+{
+ struct wd_data *uadk_data = p->compress_data;
+ uint32_t hdr_size;
+ uint8_t *buf = uadk_data->buf;
+ int ret = 0;
+
+ if (!multifd_send_prepare_common(p)) {
+ goto out;
+ }
+
+ hdr_size = p->pages->normal_num * sizeof(uint32_t);
+ /* prepare the header that stores the lengths of all compressed data */
+ prepare_next_iov(p, uadk_data->buf_hdr, hdr_size);
+
+ for (int i = 0; i < p->pages->normal_num; i++) {
+ struct wd_comp_req creq = {
+ .op_type = WD_DIR_COMPRESS,
+ .src = p->pages->block->host + p->pages->offset[i],
+ .src_len = p->page_size,
+ .dst = buf,
+ /* Set dst_len to double the src in case compressed out >= page_size */
+ .dst_len = p->page_size * 2,
+ };
+
+ if (uadk_data->handle) {
+ ret = wd_do_comp_sync(uadk_data->handle, &creq);
+ if (ret || creq.status) {
+ error_setg(errp, "multifd %u: failed compression, ret %d status %d",
+ p->id, ret, creq.status);
+ return -1;
+ }
+ if (creq.dst_len < p->page_size) {
+ uadk_data->buf_hdr[i] = cpu_to_be32(creq.dst_len);
+ prepare_next_iov(p, buf, creq.dst_len);
+ buf += creq.dst_len;
+ }
+ }
+ /*
+ * Send raw data if no UADK hardware or if compressed out >= page_size.
+ * We might be better off sending raw data if output is slightly less
+ * than page_size as well because at the receive end we can skip the
+ * decompression. But it is tricky to find the right number here.
+ */
+ if (!uadk_data->handle || creq.dst_len >= p->page_size) {
+ uadk_data->buf_hdr[i] = cpu_to_be32(p->page_size);
+ prepare_next_iov(p, p->pages->block->host + p->pages->offset[i],
+ p->page_size);
+ buf += p->page_size;
+ }
+ }
+out:
+ p->flags |= MULTIFD_FLAG_UADK;
+ multifd_send_fill_packet(p);
+ return 0;
+}
+
+/**
+ * multifd_uadk_recv_setup: setup receive side
+ *
+ * Create the compressed channel and buffer.
+ *
+ * Returns 0 for success or -1 for error
+ *
+ * @p: Params for the channel that we are using
+ * @errp: pointer to an error
+ */
+static int multifd_uadk_recv_setup(MultiFDRecvParams *p, Error **errp)
+{
+ struct wd_data *wd;
+
+ wd = multifd_uadk_init_sess(p->page_count, p->page_size, false, errp);
+ if (!wd) {
+ return -1;
+ }
+ p->compress_data = wd;
+ return 0;
+}
+
+/**
+ * multifd_uadk_recv_cleanup: cleanup receive side
+ *
+ * Close the channel and return memory.
+ *
+ * @p: Params for the channel that we are using
+ */
+static void multifd_uadk_recv_cleanup(MultiFDRecvParams *p)
+{
+ struct wd_data *wd = p->compress_data;
+
+ multifd_uadk_uninit_sess(wd);
+ p->compress_data = NULL;
+}
+
+/**
+ * multifd_uadk_recv: read the data from the channel into actual pages
+ *
+ * Read the compressed buffer, and uncompress it into the actual
+ * pages.
+ *
+ * Returns 0 for success or -1 for error
+ *
+ * @p: Params for the channel that we are using
+ * @errp: pointer to an error
+ */
+static int multifd_uadk_recv(MultiFDRecvParams *p, Error **errp)
+{
+ struct wd_data *uadk_data = p->compress_data;
+ uint32_t in_size = p->next_packet_size;
+ uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK;
+ uint32_t hdr_len = p->normal_num * sizeof(uint32_t);
+ uint32_t data_len = 0;
+ uint8_t *buf = uadk_data->buf;
+ int ret = 0;
+
+ if (flags != MULTIFD_FLAG_UADK) {
+ error_setg(errp, "multifd %u: flags received %x flags expected %x",
+ p->id, flags, MULTIFD_FLAG_ZLIB);
+ return -1;
+ }
+
+ multifd_recv_zero_page_process(p);
+ if (!p->normal_num) {
+ assert(in_size == 0);
+ return 0;
+ }
+
+ /* read compressed data lengths */
+ assert(hdr_len < in_size);
+ ret = qio_channel_read_all(p->c, (void *) uadk_data->buf_hdr,
+ hdr_len, errp);
+ if (ret != 0) {
+ return ret;
+ }
+
+ for (int i = 0; i < p->normal_num; i++) {
+ uadk_data->buf_hdr[i] = be32_to_cpu(uadk_data->buf_hdr[i]);
+ data_len += uadk_data->buf_hdr[i];
+ assert(uadk_data->buf_hdr[i] <= p->page_size);
+ }
+
+ /* read compressed data */
+ assert(in_size == hdr_len + data_len);
+ ret = qio_channel_read_all(p->c, (void *)buf, data_len, errp);
+ if (ret != 0) {
+ return ret;
+ }
+
+ for (int i = 0; i < p->normal_num; i++) {
+ struct wd_comp_req creq = {
+ .op_type = WD_DIR_DECOMPRESS,
+ .src = buf,
+ .src_len = uadk_data->buf_hdr[i],
+ .dst = p->host + p->normal[i],
+ .dst_len = p->page_size,
+ };
+
+ if (uadk_data->buf_hdr[i] == p->page_size) {
+ memcpy(p->host + p->normal[i], buf, p->page_size);
+ buf += p->page_size;
+ continue;
+ }
+
+ if (unlikely(!uadk_data->handle)) {
+ error_setg(errp, "multifd %u: UADK HW not available for decompression",
+ p->id);
+ return -1;
+ }
+
+ ret = wd_do_comp_sync(uadk_data->handle, &creq);
+ if (ret || creq.status) {
+ error_setg(errp, "multifd %u: failed decompression, ret %d status %d",
+ p->id, ret, creq.status);
+ return -1;
+ }
+ if (creq.dst_len != p->page_size) {
+ error_setg(errp, "multifd %u: decompressed length error", p->id);
+ return -1;
+ }
+ buf += uadk_data->buf_hdr[i];
+ }
+
+ return 0;
+}
+
+static MultiFDMethods multifd_uadk_ops = {
+ .send_setup = multifd_uadk_send_setup,
+ .send_cleanup = multifd_uadk_send_cleanup,
+ .send_prepare = multifd_uadk_send_prepare,
+ .recv_setup = multifd_uadk_recv_setup,
+ .recv_cleanup = multifd_uadk_recv_cleanup,
+ .recv = multifd_uadk_recv,
+};
+
+static void multifd_uadk_register(void)
+{
+ multifd_register_ops(MULTIFD_COMPRESSION_UADK, &multifd_uadk_ops);
+}
+migration_init(multifd_uadk_register);
diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c
index 737a964..2ced694 100644
--- a/migration/multifd-zlib.c
+++ b/migration/multifd-zlib.c
@@ -70,6 +70,10 @@
goto err_free_zbuff;
}
p->compress_data = z;
+
+ /* Needs 2 IOVs, one for packet header and one for compressed data */
+ p->iov = g_new0(struct iovec, 2);
+
return 0;
err_free_zbuff:
@@ -101,6 +105,9 @@
z->buf = NULL;
g_free(p->compress_data);
p->compress_data = NULL;
+
+ g_free(p->iov);
+ p->iov = NULL;
}
/**
diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c
index 256858d..ca17b7e 100644
--- a/migration/multifd-zstd.c
+++ b/migration/multifd-zstd.c
@@ -52,7 +52,6 @@
struct zstd_data *z = g_new0(struct zstd_data, 1);
int res;
- p->compress_data = z;
z->zcs = ZSTD_createCStream();
if (!z->zcs) {
g_free(z);
@@ -77,6 +76,10 @@
error_setg(errp, "multifd %u: out of memory for zbuff", p->id);
return -1;
}
+ p->compress_data = z;
+
+ /* Needs 2 IOVs, one for packet header and one for compressed data */
+ p->iov = g_new0(struct iovec, 2);
return 0;
}
@@ -98,6 +101,9 @@
z->zbuff = NULL;
g_free(p->compress_data);
p->compress_data = NULL;
+
+ g_free(p->iov);
+ p->iov = NULL;
}
/**
diff --git a/migration/multifd.c b/migration/multifd.c
index f317bff..d82885f 100644
--- a/migration/multifd.c
+++ b/migration/multifd.c
@@ -137,6 +137,13 @@
p->write_flags |= QIO_CHANNEL_WRITE_FLAG_ZERO_COPY;
}
+ if (multifd_use_packets()) {
+ /* We need one extra place for the packet header */
+ p->iov = g_new0(struct iovec, p->page_count + 1);
+ } else {
+ p->iov = g_new0(struct iovec, p->page_count);
+ }
+
return 0;
}
@@ -150,6 +157,8 @@
*/
static void nocomp_send_cleanup(MultiFDSendParams *p, Error **errp)
{
+ g_free(p->iov);
+ p->iov = NULL;
return;
}
@@ -228,6 +237,7 @@
*/
static int nocomp_recv_setup(MultiFDRecvParams *p, Error **errp)
{
+ p->iov = g_new0(struct iovec, p->page_count);
return 0;
}
@@ -240,6 +250,8 @@
*/
static void nocomp_recv_cleanup(MultiFDRecvParams *p)
{
+ g_free(p->iov);
+ p->iov = NULL;
}
/**
@@ -783,8 +795,6 @@
p->packet_len = 0;
g_free(p->packet);
p->packet = NULL;
- g_free(p->iov);
- p->iov = NULL;
multifd_send_state->ops->send_cleanup(p, errp);
return *errp == NULL;
@@ -1179,11 +1189,6 @@
p->packet = g_malloc0(p->packet_len);
p->packet->magic = cpu_to_be32(MULTIFD_MAGIC);
p->packet->version = cpu_to_be32(MULTIFD_VERSION);
-
- /* We need one extra place for the packet header */
- p->iov = g_new0(struct iovec, page_count + 1);
- } else {
- p->iov = g_new0(struct iovec, page_count);
}
p->name = g_strdup_printf("multifdsend_%d", i);
p->page_size = qemu_target_page_size();
@@ -1353,8 +1358,6 @@
p->packet_len = 0;
g_free(p->packet);
p->packet = NULL;
- g_free(p->iov);
- p->iov = NULL;
g_free(p->normal);
p->normal = NULL;
g_free(p->zero);
@@ -1602,7 +1605,6 @@
p->packet = g_malloc0(p->packet_len);
}
p->name = g_strdup_printf("multifdrecv_%d", i);
- p->iov = g_new0(struct iovec, page_count);
p->normal = g_new0(ram_addr_t, page_count);
p->zero = g_new0(ram_addr_t, page_count);
p->page_count = page_count;
diff --git a/migration/multifd.h b/migration/multifd.h
index c9d9b09..0ecd6f4 100644
--- a/migration/multifd.h
+++ b/migration/multifd.h
@@ -34,12 +34,14 @@
/* Multifd Compression flags */
#define MULTIFD_FLAG_SYNC (1 << 0)
-/* We reserve 3 bits for compression methods */
-#define MULTIFD_FLAG_COMPRESSION_MASK (7 << 1)
+/* We reserve 4 bits for compression methods */
+#define MULTIFD_FLAG_COMPRESSION_MASK (0xf << 1)
/* we need to be compatible. Before compression value was 0 */
#define MULTIFD_FLAG_NOCOMP (0 << 1)
#define MULTIFD_FLAG_ZLIB (1 << 1)
#define MULTIFD_FLAG_ZSTD (2 << 1)
+#define MULTIFD_FLAG_QPL (4 << 1)
+#define MULTIFD_FLAG_UADK (8 << 1)
/* This value needs to be a multiple of qemu_target_page_size() */
#define MULTIFD_PACKET_SIZE (512 * 1024)
diff --git a/qapi/migration.json b/qapi/migration.json
index a351fd3..470f746 100644
--- a/qapi/migration.json
+++ b/qapi/migration.json
@@ -554,11 +554,20 @@
#
# @zstd: use zstd compression method.
#
+# @qpl: use qpl compression method. Query Processing Library(qpl) is
+# based on the deflate compression algorithm and use the Intel
+# In-Memory Analytics Accelerator(IAA) accelerated compression
+# and decompression. (Since 9.1)
+#
+# @uadk: use UADK library compression method. (Since 9.1)
+#
# Since: 5.0
##
{ 'enum': 'MultiFDCompression',
'data': [ 'none', 'zlib',
- { 'name': 'zstd', 'if': 'CONFIG_ZSTD' } ] }
+ { 'name': 'zstd', 'if': 'CONFIG_ZSTD' },
+ { 'name': 'qpl', 'if': 'CONFIG_QPL' },
+ { 'name': 'uadk', 'if': 'CONFIG_UADK' } ] }
##
# @MigMode:
diff --git a/qapi/qmp-dispatch.c b/qapi/qmp-dispatch.c
index f3488af..176b549 100644
--- a/qapi/qmp-dispatch.c
+++ b/qapi/qmp-dispatch.c
@@ -212,7 +212,8 @@
* executing the command handler so that it can make progress if it
* involves an AIO_WAIT_WHILE().
*/
- aio_co_reschedule_self(qemu_get_aio_context());
+ aio_co_schedule(qemu_get_aio_context(), qemu_coroutine_self());
+ qemu_coroutine_yield();
}
monitor_set_cur(qemu_coroutine_self(), cur_mon);
@@ -226,7 +227,9 @@
* Move back to iohandler_ctx so that nested event loops for
* qemu_aio_context don't start new monitor commands.
*/
- aio_co_reschedule_self(iohandler_get_aio_context());
+ aio_co_schedule(iohandler_get_aio_context(),
+ qemu_coroutine_self());
+ qemu_coroutine_yield();
}
} else {
/*
diff --git a/qemu-io-cmds.c b/qemu-io-cmds.c
index f5d7202..e2fab57 100644
--- a/qemu-io-cmds.c
+++ b/qemu-io-cmds.c
@@ -1739,12 +1739,26 @@
{
int ret;
int64_t offset;
+ int64_t val;
unsigned int nr_zones;
++optind;
offset = cvtnum(argv[optind]);
+ if (offset < 0) {
+ print_cvtnum_err(offset, argv[optind]);
+ return offset;
+ }
++optind;
- nr_zones = cvtnum(argv[optind]);
+ val = cvtnum(argv[optind]);
+ if (val < 0) {
+ print_cvtnum_err(val, argv[optind]);
+ return val;
+ }
+ if (val > UINT_MAX) {
+ printf("Number of zones must be less than 2^32\n");
+ return -ERANGE;
+ }
+ nr_zones = val;
g_autofree BlockZoneDescriptor *zones = NULL;
zones = g_new(BlockZoneDescriptor, nr_zones);
@@ -1780,8 +1794,16 @@
int64_t offset, len;
++optind;
offset = cvtnum(argv[optind]);
+ if (offset < 0) {
+ print_cvtnum_err(offset, argv[optind]);
+ return offset;
+ }
++optind;
len = cvtnum(argv[optind]);
+ if (len < 0) {
+ print_cvtnum_err(len, argv[optind]);
+ return len;
+ }
ret = blk_zone_mgmt(blk, BLK_ZO_OPEN, offset, len);
if (ret < 0) {
printf("zone open failed: %s\n", strerror(-ret));
@@ -1805,8 +1827,16 @@
int64_t offset, len;
++optind;
offset = cvtnum(argv[optind]);
+ if (offset < 0) {
+ print_cvtnum_err(offset, argv[optind]);
+ return offset;
+ }
++optind;
len = cvtnum(argv[optind]);
+ if (len < 0) {
+ print_cvtnum_err(len, argv[optind]);
+ return len;
+ }
ret = blk_zone_mgmt(blk, BLK_ZO_CLOSE, offset, len);
if (ret < 0) {
printf("zone close failed: %s\n", strerror(-ret));
@@ -1830,8 +1860,16 @@
int64_t offset, len;
++optind;
offset = cvtnum(argv[optind]);
+ if (offset < 0) {
+ print_cvtnum_err(offset, argv[optind]);
+ return offset;
+ }
++optind;
len = cvtnum(argv[optind]);
+ if (len < 0) {
+ print_cvtnum_err(len, argv[optind]);
+ return len;
+ }
ret = blk_zone_mgmt(blk, BLK_ZO_FINISH, offset, len);
if (ret < 0) {
printf("zone finish failed: %s\n", strerror(-ret));
@@ -1855,8 +1893,16 @@
int64_t offset, len;
++optind;
offset = cvtnum(argv[optind]);
+ if (offset < 0) {
+ print_cvtnum_err(offset, argv[optind]);
+ return offset;
+ }
++optind;
len = cvtnum(argv[optind]);
+ if (len < 0) {
+ print_cvtnum_err(len, argv[optind]);
+ return len;
+ }
ret = blk_zone_mgmt(blk, BLK_ZO_RESET, offset, len);
if (ret < 0) {
printf("zone reset failed: %s\n", strerror(-ret));
diff --git a/scripts/ci/setup/ubuntu/ubuntu-2204-aarch64.yaml b/scripts/ci/setup/ubuntu/ubuntu-2204-aarch64.yaml
index 8d7d872..fd5489c 100644
--- a/scripts/ci/setup/ubuntu/ubuntu-2204-aarch64.yaml
+++ b/scripts/ci/setup/ubuntu/ubuntu-2204-aarch64.yaml
@@ -49,7 +49,6 @@
- libglusterfs-dev
- libgnutls28-dev
- libgtk-3-dev
- - libibumad-dev
- libibverbs-dev
- libiscsi-dev
- libjemalloc-dev
diff --git a/scripts/ci/setup/ubuntu/ubuntu-2204-s390x.yaml b/scripts/ci/setup/ubuntu/ubuntu-2204-s390x.yaml
index 16050a5..afa0450 100644
--- a/scripts/ci/setup/ubuntu/ubuntu-2204-s390x.yaml
+++ b/scripts/ci/setup/ubuntu/ubuntu-2204-s390x.yaml
@@ -49,7 +49,6 @@
- libglusterfs-dev
- libgnutls28-dev
- libgtk-3-dev
- - libibumad-dev
- libibverbs-dev
- libiscsi-dev
- libjemalloc-dev
diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh
index 6ce5a8b..58d49a4 100644
--- a/scripts/meson-buildoptions.sh
+++ b/scripts/meson-buildoptions.sh
@@ -220,6 +220,8 @@
printf "%s\n" ' Xen PCI passthrough support'
printf "%s\n" ' xkbcommon xkbcommon support'
printf "%s\n" ' zstd zstd compression support'
+ printf "%s\n" ' qpl Query Processing Library support'
+ printf "%s\n" ' uadk UADK Library support'
}
_meson_option_parse() {
case $1 in
@@ -558,6 +560,10 @@
--disable-xkbcommon) printf "%s" -Dxkbcommon=disabled ;;
--enable-zstd) printf "%s" -Dzstd=enabled ;;
--disable-zstd) printf "%s" -Dzstd=disabled ;;
+ --enable-qpl) printf "%s" -Dqpl=enabled ;;
+ --disable-qpl) printf "%s" -Dqpl=disabled ;;
+ --enable-uadk) printf "%s" -Duadk=enabled ;;
+ --disable-uadk) printf "%s" -Duadk=disabled ;;
*) return 1 ;;
esac
}
diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__init__.py
index b887540..bc03238 100644
--- a/scripts/tracetool/__init__.py
+++ b/scripts/tracetool/__init__.py
@@ -301,18 +301,14 @@
if fmt.endswith(r'\n"'):
raise ValueError("Event format must not end with a newline "
"character")
+ if '\\n' in fmt:
+ raise ValueError("Event format must not use new line character")
if len(fmt_trans) > 0:
fmt = [fmt_trans, fmt]
args = Arguments.build(groups["args"])
- event = Event(name, props, fmt, args, lineno, filename)
-
- # add implicit arguments when using the 'vcpu' property
- import tracetool.vcpu
- event = tracetool.vcpu.transform_event(event)
-
- return event
+ return Event(name, props, fmt, args, lineno, filename)
def __repr__(self):
"""Evaluable string representation for this object."""
diff --git a/scripts/tracetool/vcpu.py b/scripts/tracetool/vcpu.py
deleted file mode 100644
index d232cb1..0000000
--- a/scripts/tracetool/vcpu.py
+++ /dev/null
@@ -1,59 +0,0 @@
-# -*- coding: utf-8 -*-
-
-"""
-Generic management for the 'vcpu' property.
-
-"""
-
-__author__ = "Lluís Vilanova <vilanova@ac.upc.edu>"
-__copyright__ = "Copyright 2016, Lluís Vilanova <vilanova@ac.upc.edu>"
-__license__ = "GPL version 2 or (at your option) any later version"
-
-__maintainer__ = "Stefan Hajnoczi"
-__email__ = "stefanha@redhat.com"
-
-
-from tracetool import Arguments, try_import
-
-
-def transform_event(event):
- """Transform event to comply with the 'vcpu' property (if present)."""
- if "vcpu" in event.properties:
- event.args = Arguments([("void *", "__cpu"), event.args])
- fmt = "\"cpu=%p \""
- event.fmt = fmt + event.fmt
- return event
-
-
-def transform_args(format, event, *args, **kwargs):
- """Transforms the arguments to suit the specified format.
-
- The format module must implement function 'vcpu_args', which receives the
- implicit arguments added by the 'vcpu' property, and must return suitable
- arguments for the given format.
-
- The function is only called for events with the 'vcpu' property.
-
- Parameters
- ==========
- format : str
- Format module name.
- event : Event
- args, kwargs
- Passed to 'vcpu_transform_args'.
-
- Returns
- =======
- Arguments
- The transformed arguments, including the non-implicit ones.
-
- """
- if "vcpu" in event.properties:
- ok, func = try_import("tracetool.format." + format,
- "vcpu_transform_args")
- assert ok
- assert func
- return Arguments([func(event.args[:1], *args, **kwargs),
- event.args[1:]])
- else:
- return event.args
diff --git a/system/physmem.c b/system/physmem.c
index b7847db..33d09f7 100644
--- a/system/physmem.c
+++ b/system/physmem.c
@@ -2231,13 +2231,14 @@
*/
if (xen_mr_is_memory(block->mr)) {
return xen_map_cache(block->mr, block->offset + addr,
- len, lock, lock,
- is_write);
+ len, block->offset,
+ lock, lock, is_write);
}
block->host = xen_map_cache(block->mr, block->offset,
- block->max_length, 1,
- lock, is_write);
+ block->max_length,
+ block->offset,
+ 1, lock, is_write);
}
return ramblock_ptr(block, addr);
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index cec0181..3a20644 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -311,6 +311,17 @@
self, 'boot', '## Loading kernel from FIT Image')
self.wait_for_console_pattern('Starting kernel ...')
+ def do_test_aarch64_aspeed_sdk_start(self, image):
+ self.vm.set_console()
+ self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw')
+
+ self.vm.launch()
+
+ self.wait_for_console_pattern('U-Boot 2023.10')
+ self.wait_for_console_pattern('## Loading kernel from FIT Image')
+ self.wait_for_console_pattern('Starting kernel ...')
+ self.wait_for_console_pattern("systemd[1]: Hostname set to")
+
@skipUnless(os.getenv('QEMU_TEST_FLAKY_TESTS'), 'Test is unstable on GitLab')
def test_arm_ast2500_evb_sdk(self):
@@ -375,3 +386,54 @@
'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32');
year = time.strftime("%Y")
self.ssh_command_output_contains('/sbin/hwclock -f /dev/rtc1', year);
+
+ def test_aarch64_ast2700_evb_sdk_v09_01(self):
+ """
+ :avocado: tags=arch:aarch64
+ :avocado: tags=machine:ast2700-evb
+ """
+
+ image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
+ 'download/v09.01/ast2700-default-obmc.tar.gz')
+ image_hash = 'b1cc0fd73c7650d34c9c8459a243f52a91e9e27144b8608b2645ab19461d1e07'
+ image_path = self.fetch_asset(image_url, asset_hash=image_hash,
+ algorithm='sha256')
+ archive.extract(image_path, self.workdir)
+
+ num_cpu = 4
+ image_dir = self.workdir + '/ast2700-default/'
+ uboot_size = os.path.getsize(image_dir + 'u-boot-nodtb.bin')
+ uboot_dtb_load_addr = hex(0x400000000 + uboot_size)
+
+ load_images_list = [
+ {
+ 'addr': '0x400000000',
+ 'file': image_dir + 'u-boot-nodtb.bin'
+ },
+ {
+ 'addr': str(uboot_dtb_load_addr),
+ 'file': image_dir + 'u-boot.dtb'
+ },
+ {
+ 'addr': '0x430000000',
+ 'file': image_dir + 'bl31.bin'
+ },
+ {
+ 'addr': '0x430080000',
+ 'file': image_dir + 'optee/tee-raw.bin'
+ }
+ ]
+
+ for load_image in load_images_list:
+ addr = load_image['addr']
+ file = load_image['file']
+ self.vm.add_args('-device',
+ f'loader,force-raw=on,addr={addr},file={file}')
+
+ for i in range(num_cpu):
+ self.vm.add_args('-device',
+ f'loader,addr=0x430000000,cpu-num={i}')
+
+ self.vm.add_args('-smp', str(num_cpu))
+ self.do_test_aarch64_aspeed_sdk_start(image_dir + 'image-bmc')
+
diff --git a/tests/avocado/machine_loongarch.py b/tests/avocado/machine_loongarch.py
index 7d8a3c1..8de308f 100644
--- a/tests/avocado/machine_loongarch.py
+++ b/tests/avocado/machine_loongarch.py
@@ -27,18 +27,18 @@
"""
kernel_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
- 'releases/download/binary-files/vmlinuz.efi')
+ 'releases/download/2024-05-30/vmlinuz.efi')
kernel_hash = '951b485b16e3788b6db03a3e1793c067009e31a2'
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
initrd_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
- 'releases/download/binary-files/ramdisk')
+ 'releases/download/2024-05-30/ramdisk')
initrd_hash = 'c67658d9b2a447ce7db2f73ba3d373c9b2b90ab2'
initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
bios_url = ('https://github.com/yangxiaojuan-loongson/qemu-binary/'
- 'releases/download/binary-files/QEMU_EFI.fd')
- bios_hash = ('dfc1bfba4853cd763b9d392d0031827e8addbca8')
+ 'releases/download/2024-05-30/QEMU_EFI.fd')
+ bios_hash = ('f4d0966b5117d4cd82327c050dd668741046be69')
bios_path = self.fetch_asset(bios_url, asset_hash=bios_hash)
self.vm.set_console()
diff --git a/tests/docker/dockerfiles/debian-amd64-cross.docker b/tests/docker/dockerfiles/debian-amd64-cross.docker
index f8c61d1..8058695 100644
--- a/tests/docker/dockerfiles/debian-amd64-cross.docker
+++ b/tests/docker/dockerfiles/debian-amd64-cross.docker
@@ -105,7 +105,6 @@
libglusterfs-dev:amd64 \
libgnutls28-dev:amd64 \
libgtk-3-dev:amd64 \
- libibumad-dev:amd64 \
libibverbs-dev:amd64 \
libiscsi-dev:amd64 \
libjemalloc-dev:amd64 \
diff --git a/tests/docker/dockerfiles/debian-arm64-cross.docker b/tests/docker/dockerfiles/debian-arm64-cross.docker
index 6510872..15457d7 100644
--- a/tests/docker/dockerfiles/debian-arm64-cross.docker
+++ b/tests/docker/dockerfiles/debian-arm64-cross.docker
@@ -105,7 +105,6 @@
libglusterfs-dev:arm64 \
libgnutls28-dev:arm64 \
libgtk-3-dev:arm64 \
- libibumad-dev:arm64 \
libibverbs-dev:arm64 \
libiscsi-dev:arm64 \
libjemalloc-dev:arm64 \
diff --git a/tests/docker/dockerfiles/debian-armel-cross.docker b/tests/docker/dockerfiles/debian-armel-cross.docker
index f227d42..c26ffc2 100644
--- a/tests/docker/dockerfiles/debian-armel-cross.docker
+++ b/tests/docker/dockerfiles/debian-armel-cross.docker
@@ -108,7 +108,6 @@
libglusterfs-dev:armel \
libgnutls28-dev:armel \
libgtk-3-dev:armel \
- libibumad-dev:armel \
libibverbs-dev:armel \
libiscsi-dev:armel \
libjemalloc-dev:armel \
diff --git a/tests/docker/dockerfiles/debian-armhf-cross.docker b/tests/docker/dockerfiles/debian-armhf-cross.docker
index 58bdf07..8f87656 100644
--- a/tests/docker/dockerfiles/debian-armhf-cross.docker
+++ b/tests/docker/dockerfiles/debian-armhf-cross.docker
@@ -105,7 +105,6 @@
libglusterfs-dev:armhf \
libgnutls28-dev:armhf \
libgtk-3-dev:armhf \
- libibumad-dev:armhf \
libibverbs-dev:armhf \
libiscsi-dev:armhf \
libjemalloc-dev:armhf \
diff --git a/tests/docker/dockerfiles/debian-i686-cross.docker b/tests/docker/dockerfiles/debian-i686-cross.docker
index 9f4102b..f1e5b0b 100644
--- a/tests/docker/dockerfiles/debian-i686-cross.docker
+++ b/tests/docker/dockerfiles/debian-i686-cross.docker
@@ -108,7 +108,6 @@
libglusterfs-dev:i386 \
libgnutls28-dev:i386 \
libgtk-3-dev:i386 \
- libibumad-dev:i386 \
libibverbs-dev:i386 \
libiscsi-dev:i386 \
libjemalloc-dev:i386 \
diff --git a/tests/docker/dockerfiles/debian-mips64el-cross.docker b/tests/docker/dockerfiles/debian-mips64el-cross.docker
index c861c3b..59c4c68 100644
--- a/tests/docker/dockerfiles/debian-mips64el-cross.docker
+++ b/tests/docker/dockerfiles/debian-mips64el-cross.docker
@@ -107,7 +107,6 @@
libglusterfs-dev:mips64el \
libgnutls28-dev:mips64el \
libgtk-3-dev:mips64el \
- libibumad-dev:mips64el \
libibverbs-dev:mips64el \
libiscsi-dev:mips64el \
libjemalloc-dev:mips64el \
diff --git a/tests/docker/dockerfiles/debian-mipsel-cross.docker b/tests/docker/dockerfiles/debian-mipsel-cross.docker
index fe94153..880c774 100644
--- a/tests/docker/dockerfiles/debian-mipsel-cross.docker
+++ b/tests/docker/dockerfiles/debian-mipsel-cross.docker
@@ -107,7 +107,6 @@
libglusterfs-dev:mipsel \
libgnutls28-dev:mipsel \
libgtk-3-dev:mipsel \
- libibumad-dev:mipsel \
libibverbs-dev:mipsel \
libiscsi-dev:mipsel \
libjemalloc-dev:mipsel \
diff --git a/tests/docker/dockerfiles/debian-ppc64el-cross.docker b/tests/docker/dockerfiles/debian-ppc64el-cross.docker
index 35c8ff0..1d55b95 100644
--- a/tests/docker/dockerfiles/debian-ppc64el-cross.docker
+++ b/tests/docker/dockerfiles/debian-ppc64el-cross.docker
@@ -105,7 +105,6 @@
libglusterfs-dev:ppc64el \
libgnutls28-dev:ppc64el \
libgtk-3-dev:ppc64el \
- libibumad-dev:ppc64el \
libibverbs-dev:ppc64el \
libiscsi-dev:ppc64el \
libjemalloc-dev:ppc64el \
diff --git a/tests/docker/dockerfiles/debian-s390x-cross.docker b/tests/docker/dockerfiles/debian-s390x-cross.docker
index bef9dff..62ccda6 100644
--- a/tests/docker/dockerfiles/debian-s390x-cross.docker
+++ b/tests/docker/dockerfiles/debian-s390x-cross.docker
@@ -105,7 +105,6 @@
libglusterfs-dev:s390x \
libgnutls28-dev:s390x \
libgtk-3-dev:s390x \
- libibumad-dev:s390x \
libibverbs-dev:s390x \
libiscsi-dev:s390x \
libjemalloc-dev:s390x \
diff --git a/tests/docker/dockerfiles/debian.docker b/tests/docker/dockerfiles/debian.docker
index 63d7aac..0d1d401 100644
--- a/tests/docker/dockerfiles/debian.docker
+++ b/tests/docker/dockerfiles/debian.docker
@@ -55,7 +55,6 @@
libglusterfs-dev \
libgnutls28-dev \
libgtk-3-dev \
- libibumad-dev \
libibverbs-dev \
libiscsi-dev \
libjemalloc-dev \
diff --git a/tests/docker/dockerfiles/ubuntu2204.docker b/tests/docker/dockerfiles/ubuntu2204.docker
index febd25b..beeb44f 100644
--- a/tests/docker/dockerfiles/ubuntu2204.docker
+++ b/tests/docker/dockerfiles/ubuntu2204.docker
@@ -55,7 +55,6 @@
libglusterfs-dev \
libgnutls28-dev \
libgtk-3-dev \
- libibumad-dev \
libibverbs-dev \
libiscsi-dev \
libjemalloc-dev \
diff --git a/tests/lcitool/projects/qemu.yml b/tests/lcitool/projects/qemu.yml
index 070d7f4..0c85784 100644
--- a/tests/lcitool/projects/qemu.yml
+++ b/tests/lcitool/projects/qemu.yml
@@ -47,7 +47,6 @@
- libfdt
- libffi
- libgcrypt
- - libibumad
- libibverbs
- libiscsi
- libjemalloc
diff --git a/tests/migration/Makefile b/tests/migration/Makefile
index 13e99b1..2c5ee28 100644
--- a/tests/migration/Makefile
+++ b/tests/migration/Makefile
@@ -5,7 +5,7 @@
# See the COPYING file in the top-level directory.
#
-TARGET_LIST = i386 aarch64 s390x
+TARGET_LIST = i386 aarch64 s390x ppc64
SRC_PATH = ../..
diff --git a/tests/migration/migration-test.h b/tests/migration/migration-test.h
index 68512c0..194df7d 100644
--- a/tests/migration/migration-test.h
+++ b/tests/migration/migration-test.h
@@ -22,6 +22,7 @@
/* PPC */
#define PPC_TEST_MEM_START (1 * 1024 * 1024)
#define PPC_TEST_MEM_END (100 * 1024 * 1024)
+#define PPC_H_PUT_TERM_CHAR 0x58
/* ARM */
#define ARM_TEST_MEM_START (0x40000000 + 1 * 1024 * 1024)
diff --git a/tests/migration/ppc64/Makefile b/tests/migration/ppc64/Makefile
new file mode 100644
index 0000000..a3a2d98
--- /dev/null
+++ b/tests/migration/ppc64/Makefile
@@ -0,0 +1,15 @@
+.PHONY: all clean
+all: a-b-kernel.h
+
+a-b-kernel.h: ppc64.kernel
+ echo "$$__note" > $@
+ xxd -i $< | sed -e 's/.*int.*//' >> $@
+
+ppc64.kernel: ppc64.elf
+ $(CROSS_PREFIX)objcopy -O binary -S $< $@
+
+ppc64.elf: a-b-kernel.S
+ $(CROSS_PREFIX)gcc -static -o $@ -nostdlib -Wl,--build-id=none $<
+
+clean:
+ $(RM) *.kernel *.elf
diff --git a/tests/migration/ppc64/a-b-kernel.S b/tests/migration/ppc64/a-b-kernel.S
new file mode 100644
index 0000000..0613a8d
--- /dev/null
+++ b/tests/migration/ppc64/a-b-kernel.S
@@ -0,0 +1,66 @@
+#
+# Copyright (c) 2024 IBM, Inc
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or later.
+# See the COPYING file in the top-level directory.
+
+#include "../migration-test.h"
+
+.section .text
+
+.macro print ch
+ li %r3,PPC_H_PUT_TERM_CHAR
+ li %r4,0
+ li %r5,1
+ li %r6,\ch
+ sldi %r6,%r6,56
+ sc 1
+.endm
+
+ .globl _start
+_start:
+. = 0x100
+ /*
+ * Enter 64-bit mode. Not necessary because the test uses 32-bit
+ * addresses, but those constants could easily be changed and break
+ * in 32-bit mode.
+ */
+ mfmsr %r9
+ li %r10,-1
+ rldimi %r9,%r10,63,0
+ mtmsrd %r9
+
+ /*
+ * Set up test memory region. Non-volatiles are used because the
+ * hcall can clobber regs.
+ * r20 - start address
+ * r21 - number of pages
+ */
+ lis %r20,PPC_TEST_MEM_START@h
+ ori %r20,%r20,PPC_TEST_MEM_START@l
+ lis %r9,PPC_TEST_MEM_END@h
+ ori %r9,%r9,PPC_TEST_MEM_END@l
+ subf %r21,%r20,%r9
+ li %r10,TEST_MEM_PAGE_SIZE
+ divd %r21,%r21,%r10
+
+ print 'A'
+
+ li %r3,0
+ mr %r9,%r20
+ mtctr %r21
+1: stb %r3,0(%r9)
+ addi %r9,%r9,TEST_MEM_PAGE_SIZE
+ bdnz 1b
+
+loop:
+ mr %r9,%r20
+ mtctr %r21
+1: lbz %r3,0(%r9)
+ addi %r3,%r3,1
+ stb %r3,0(%r9)
+ addi %r9,%r9,TEST_MEM_PAGE_SIZE
+ bdnz 1b
+
+ print 'B'
+ b loop
diff --git a/tests/migration/ppc64/a-b-kernel.h b/tests/migration/ppc64/a-b-kernel.h
new file mode 100644
index 0000000..673317e
--- /dev/null
+++ b/tests/migration/ppc64/a-b-kernel.h
@@ -0,0 +1,42 @@
+/* This file is automatically generated from the assembly file in
+ * tests/migration/ppc64. Edit that file and then run "make all"
+ * inside tests/migration to update, and then remember to send both
+ * the header and the assembler differences in your patch submission.
+ */
+unsigned char ppc64_kernel[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x7d, 0x20, 0x00, 0xa6, 0x39, 0x40, 0xff, 0xff,
+ 0x79, 0x49, 0xf8, 0x0e, 0x7d, 0x20, 0x01, 0x64, 0x3e, 0x80, 0x00, 0x10,
+ 0x62, 0x94, 0x00, 0x00, 0x3d, 0x20, 0x06, 0x40, 0x61, 0x29, 0x00, 0x00,
+ 0x7e, 0xb4, 0x48, 0x50, 0x39, 0x40, 0x10, 0x00, 0x7e, 0xb5, 0x53, 0xd2,
+ 0x38, 0x60, 0x00, 0x58, 0x38, 0x80, 0x00, 0x00, 0x38, 0xa0, 0x00, 0x01,
+ 0x38, 0xc0, 0x00, 0x41, 0x78, 0xc6, 0xc1, 0xc6, 0x44, 0x00, 0x00, 0x22,
+ 0x38, 0x60, 0x00, 0x00, 0x7e, 0x89, 0xa3, 0x78, 0x7e, 0xa9, 0x03, 0xa6,
+ 0x98, 0x69, 0x00, 0x00, 0x39, 0x29, 0x10, 0x00, 0x42, 0x00, 0xff, 0xf8,
+ 0x7e, 0x89, 0xa3, 0x78, 0x7e, 0xa9, 0x03, 0xa6, 0x88, 0x69, 0x00, 0x00,
+ 0x38, 0x63, 0x00, 0x01, 0x98, 0x69, 0x00, 0x00, 0x39, 0x29, 0x10, 0x00,
+ 0x42, 0x00, 0xff, 0xf0, 0x38, 0x60, 0x00, 0x58, 0x38, 0x80, 0x00, 0x00,
+ 0x38, 0xa0, 0x00, 0x01, 0x38, 0xc0, 0x00, 0x42, 0x78, 0xc6, 0xc1, 0xc6,
+ 0x44, 0x00, 0x00, 0x22, 0x4b, 0xff, 0xff, 0xcc
+};
+
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index df389ad..3b92fa5 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -15,7 +15,7 @@
#include "qemu/osdep.h"
#include "libqtest.h"
-#include "libqos/libqos-spapr.h"
+#include "ppc-util.h"
static const uint8_t bios_avr[] = {
0x88, 0xe0, /* ldi r24, 0x08 */
diff --git a/tests/qtest/libqos/libqos-spapr.h b/tests/qtest/libqos/libqos-spapr.h
index e4483c1..a446276 100644
--- a/tests/qtest/libqos/libqos-spapr.h
+++ b/tests/qtest/libqos/libqos-spapr.h
@@ -9,11 +9,4 @@
G_GNUC_PRINTF(1, 2);
void qtest_spapr_shutdown(QOSState *qs);
-/* List of capabilities needed to silence warnings with TCG */
-#define PSERIES_DEFAULT_CAPABILITIES \
- "cap-cfpc=broken," \
- "cap-sbbc=broken," \
- "cap-ibs=broken," \
- "cap-ccf-assist=off,"
-
#endif
diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c
index d8f80d3..18e2f7f 100644
--- a/tests/qtest/libqtest.c
+++ b/tests/qtest/libqtest.c
@@ -37,6 +37,7 @@
#include "qapi/qmp/qjson.h"
#include "qapi/qmp/qlist.h"
#include "qapi/qmp/qstring.h"
+#include "qapi/qmp/qbool.h"
#define MAX_IRQ 256
@@ -1471,6 +1472,12 @@
char *alias;
};
+struct CpuModel {
+ char *name;
+ char *alias_of;
+ bool deprecated;
+};
+
static void qtest_free_machine_list(struct MachInfo *machines)
{
if (machines) {
@@ -1550,6 +1557,82 @@
return machines;
}
+static struct CpuModel *qtest_get_cpu_models(void)
+{
+ static struct CpuModel *cpus;
+ QDict *response, *minfo;
+ QList *list;
+ const QListEntry *p;
+ QObject *qobj;
+ QString *qstr;
+ QBool *qbool;
+ QTestState *qts;
+ int idx;
+
+ if (cpus) {
+ return cpus;
+ }
+
+ silence_spawn_log = !g_test_verbose();
+
+ qts = qtest_init_with_env(NULL, "-machine none");
+ response = qtest_qmp(qts, "{ 'execute': 'query-cpu-definitions' }");
+ g_assert(response);
+ list = qdict_get_qlist(response, "return");
+ g_assert(list);
+
+ cpus = g_new0(struct CpuModel, qlist_size(list) + 1);
+
+ for (p = qlist_first(list), idx = 0; p; p = qlist_next(p), idx++) {
+ minfo = qobject_to(QDict, qlist_entry_obj(p));
+ g_assert(minfo);
+
+ qobj = qdict_get(minfo, "name");
+ g_assert(qobj);
+ qstr = qobject_to(QString, qobj);
+ g_assert(qstr);
+ cpus[idx].name = g_strdup(qstring_get_str(qstr));
+
+ qobj = qdict_get(minfo, "alias_of");
+ if (qobj) { /* old machines do not report aliases */
+ qstr = qobject_to(QString, qobj);
+ g_assert(qstr);
+ cpus[idx].alias_of = g_strdup(qstring_get_str(qstr));
+ } else {
+ cpus[idx].alias_of = NULL;
+ }
+
+ qobj = qdict_get(minfo, "deprecated");
+ qbool = qobject_to(QBool, qobj);
+ g_assert(qbool);
+ cpus[idx].deprecated = qbool_get_bool(qbool);
+ }
+
+ qtest_quit(qts);
+ qobject_unref(response);
+
+ silence_spawn_log = false;
+
+ return cpus;
+}
+
+bool qtest_has_cpu_model(const char *cpu)
+{
+ struct CpuModel *cpus;
+ int i;
+
+ cpus = qtest_get_cpu_models();
+
+ for (i = 0; cpus[i].name != NULL; i++) {
+ if (g_str_equal(cpu, cpus[i].name) ||
+ (cpus[i].alias_of && g_str_equal(cpu, cpus[i].alias_of))) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
void qtest_cb_for_every_machine(void (*cb)(const char *machine),
bool skip_old_versioned)
{
diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h
index 6e3d352..beb96b1 100644
--- a/tests/qtest/libqtest.h
+++ b/tests/qtest/libqtest.h
@@ -950,6 +950,14 @@
bool qtest_has_machine_with_env(const char *var, const char *machine);
/**
+ * qtest_has_cpu_model:
+ * @cpu: The cpu to look for
+ *
+ * Returns: true if the cpu is available in the target binary.
+ */
+bool qtest_has_cpu_model(const char *cpu);
+
+/**
* qtest_has_device:
* @device: The device to look for
*
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index b7e3406..0dccb4b 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-test.c
@@ -21,6 +21,7 @@
#include "chardev/char.h"
#include "crypto/tlscredspsk.h"
#include "qapi/qmp/qlist.h"
+#include "ppc-util.h"
#include "migration-helpers.h"
#include "tests/migration/migration-test.h"
@@ -127,6 +128,7 @@
*/
#include "tests/migration/i386/a-b-bootblock.h"
#include "tests/migration/aarch64/a-b-kernel.h"
+#include "tests/migration/ppc64/a-b-kernel.h"
#include "tests/migration/s390x/a-b-bios.h"
static void bootfile_create(char *dir, bool suspend_me)
@@ -146,10 +148,8 @@
content = s390x_elf;
len = sizeof(s390x_elf);
} else if (strcmp(arch, "ppc64") == 0) {
- /*
- * sane architectures can be programmed at the boot prompt
- */
- return;
+ content = ppc64_kernel;
+ len = sizeof(ppc64_kernel);
} else if (strcmp(arch, "aarch64") == 0) {
content = aarch64_kernel;
len = sizeof(aarch64_kernel);
@@ -180,29 +180,10 @@
{
g_autofree char *serialpath = g_strdup_printf("%s/%s", tmpfs, side);
FILE *serialfile = fopen(serialpath, "r");
- const char *arch = qtest_get_arch();
- int started = (strcmp(side, "src_serial") == 0 &&
- strcmp(arch, "ppc64") == 0) ? 0 : 1;
do {
int readvalue = fgetc(serialfile);
- if (!started) {
- /* SLOF prints its banner before starting test,
- * to ignore it, mark the start of the test with '_',
- * ignore all characters until this marker
- */
- switch (readvalue) {
- case '_':
- started = 1;
- break;
- case EOF:
- fseek(serialfile, 0, SEEK_SET);
- usleep(1000);
- break;
- }
- continue;
- }
switch (readvalue) {
case 'A':
/* Fine */
@@ -214,8 +195,6 @@
return;
case EOF:
- started = (strcmp(side, "src_serial") == 0 &&
- strcmp(arch, "ppc64") == 0) ? 0 : 1;
fseek(serialfile, 0, SEEK_SET);
usleep(1000);
break;
@@ -736,13 +715,11 @@
memory_size = "256M";
start_address = PPC_TEST_MEM_START;
end_address = PPC_TEST_MEM_END;
- arch_source = g_strdup_printf("-prom-env 'use-nvramrc?=true' -prom-env "
- "'nvramrc=hex .\" _\" begin %x %x "
- "do i c@ 1 + i c! 1000 +loop .\" B\" 0 "
- "until'", end_address, start_address);
machine_alias = "pseries";
machine_opts = "vsmt=8";
- arch_opts = g_strdup("-nodefaults");
+ arch_opts = g_strdup_printf(
+ "-nodefaults -machine " PSERIES_DEFAULT_CAPABILITIES " "
+ "-bios %s", bootpath);
} else if (strcmp(arch, "aarch64") == 0) {
memory_size = "150M";
machine_alias = "virt";
@@ -2661,6 +2638,23 @@
}
#endif /* CONFIG_ZSTD */
+#ifdef CONFIG_QPL
+static void *
+test_migrate_precopy_tcp_multifd_qpl_start(QTestState *from,
+ QTestState *to)
+{
+ return test_migrate_precopy_tcp_multifd_start_common(from, to, "qpl");
+}
+#endif /* CONFIG_QPL */
+#ifdef CONFIG_UADK
+static void *
+test_migrate_precopy_tcp_multifd_uadk_start(QTestState *from,
+ QTestState *to)
+{
+ return test_migrate_precopy_tcp_multifd_start_common(from, to, "uadk");
+}
+#endif /* CONFIG_UADK */
+
static void test_multifd_tcp_uri_none(void)
{
MigrateCommon args = {
@@ -2741,6 +2735,28 @@
}
#endif
+#ifdef CONFIG_QPL
+static void test_multifd_tcp_qpl(void)
+{
+ MigrateCommon args = {
+ .listen_uri = "defer",
+ .start_hook = test_migrate_precopy_tcp_multifd_qpl_start,
+ };
+ test_precopy_common(&args);
+}
+#endif
+
+#ifdef CONFIG_UADK
+static void test_multifd_tcp_uadk(void)
+{
+ MigrateCommon args = {
+ .listen_uri = "defer",
+ .start_hook = test_migrate_precopy_tcp_multifd_uadk_start,
+ };
+ test_precopy_common(&args);
+}
+#endif
+
#ifdef CONFIG_GNUTLS
static void *
test_migrate_multifd_tcp_tls_psk_start_match(QTestState *from,
@@ -3452,19 +3468,9 @@
#endif
/*
- * On ppc64, the test only works with kvm-hv, but not with kvm-pr and TCG
- * is touchy due to race conditions on dirty bits (especially on PPC for
- * some reason)
- */
- if (g_str_equal(arch, "ppc64") &&
- (!has_kvm || access("/sys/module/kvm_hv", F_OK))) {
- g_test_message("Skipping tests: kvm_hv not available");
- goto test_add_done;
- }
-
- /*
- * Similar to ppc64, s390x seems to be touchy with TCG, so disable it
- * there until the problems are resolved
+ * On s390x with TCG, migration is observed to hang due to the 'pending'
+ * state of the flic interrupt controller not being migrated or
+ * reconstructed post-migration. Disable it until the problem is resolved.
*/
if (g_str_equal(arch, "s390x") && !has_kvm) {
g_test_message("Skipping tests: s390x host with KVM is required");
@@ -3626,6 +3632,14 @@
migration_test_add("/migration/multifd/tcp/plain/zstd",
test_multifd_tcp_zstd);
#endif
+#ifdef CONFIG_QPL
+ migration_test_add("/migration/multifd/tcp/plain/qpl",
+ test_multifd_tcp_qpl);
+#endif
+#ifdef CONFIG_UADK
+ migration_test_add("/migration/multifd/tcp/plain/uadk",
+ test_multifd_tcp_uadk);
+#endif
#ifdef CONFIG_GNUTLS
migration_test_add("/migration/multifd/tcp/tls/psk/match",
test_multifd_tcp_tls_psk_match);
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
index 5518f65..ede4189 100644
--- a/tests/qtest/numa-test.c
+++ b/tests/qtest/numa-test.c
@@ -125,7 +125,8 @@
QTestState *qts;
g_autofree char *cli = NULL;
- cli = make_cli(data, "-cpu pentium -machine smp.cpus=8,smp.sockets=2,smp.cores=2,smp.threads=2 "
+ cli = make_cli(data,
+ "-cpu max -machine smp.cpus=8,smp.sockets=2,smp.cores=2,smp.threads=2 "
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
"-numa cpu,node-id=1,socket-id=0 "
"-numa cpu,node-id=0,socket-id=1,core-id=0 "
diff --git a/tests/qtest/ppc-util.h b/tests/qtest/ppc-util.h
new file mode 100644
index 0000000..f68ee93
--- /dev/null
+++ b/tests/qtest/ppc-util.h
@@ -0,0 +1,19 @@
+/*
+ * PowerPC misc useful things
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef PPC_UTIL_H
+#define PPC_UTIL_H
+
+/* List of capabilities needed to silence warnings with TCG */
+#define PSERIES_DEFAULT_CAPABILITIES \
+ "cap-cfpc=broken," \
+ "cap-sbbc=broken," \
+ "cap-ibs=broken," \
+ "cap-ccf-assist=off,"
+
+#endif /* PPC_UTIL_H */
diff --git a/tests/qtest/prom-env-test.c b/tests/qtest/prom-env-test.c
index 39ccb59..1470510 100644
--- a/tests/qtest/prom-env-test.c
+++ b/tests/qtest/prom-env-test.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "libqtest.h"
-#include "libqos/libqos-spapr.h"
+#include "ppc-util.h"
#define MAGIC 0xcafec0de
#define ADDRESS 0x4000
diff --git a/tests/qtest/pxe-test.c b/tests/qtest/pxe-test.c
index e4b4822..a3f900f 100644
--- a/tests/qtest/pxe-test.c
+++ b/tests/qtest/pxe-test.c
@@ -16,7 +16,7 @@
#include <glib/gstdio.h>
#include "libqtest.h"
#include "boot-sector.h"
-#include "libqos/libqos-spapr.h"
+#include "ppc-util.h"
#define NETNAME "net0"
diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpuid-compat.c
index 6a39454..b9e7e5e 100644
--- a/tests/qtest/test-x86-cpuid-compat.c
+++ b/tests/qtest/test-x86-cpuid-compat.c
@@ -67,10 +67,29 @@
g_free(path);
}
-static void add_cpuid_test(const char *name, const char *cmdline,
+static void add_cpuid_test(const char *name, const char *cpu,
+ const char *cpufeat, const char *machine,
const char *property, int64_t expected_value)
{
CpuidTestArgs *args = g_new0(CpuidTestArgs, 1);
+ char *cmdline;
+ char *save;
+
+ if (!qtest_has_cpu_model(cpu)) {
+ return;
+ }
+ cmdline = g_strdup_printf("-cpu %s", cpu);
+
+ if (cpufeat) {
+ save = cmdline;
+ cmdline = g_strdup_printf("%s,%s", cmdline, cpufeat);
+ g_free(save);
+ }
+ if (machine) {
+ save = cmdline;
+ cmdline = g_strdup_printf("-machine %s %s", machine, cmdline);
+ g_free(save);
+ }
args->cmdline = cmdline;
args->property = property;
args->expected_value = expected_value;
@@ -149,12 +168,24 @@
* either "feature-words" or "filtered-features", when running QEMU
* using cmdline
*/
-static FeatureTestArgs *add_feature_test(const char *name, const char *cmdline,
- uint32_t eax, uint32_t ecx,
- const char *reg, int bitnr,
- bool expected_value)
+static void add_feature_test(const char *name, const char *cpu,
+ const char *cpufeat, uint32_t eax,
+ uint32_t ecx, const char *reg,
+ int bitnr, bool expected_value)
{
FeatureTestArgs *args = g_new0(FeatureTestArgs, 1);
+ char *cmdline;
+
+ if (!qtest_has_cpu_model(cpu)) {
+ return;
+ }
+
+ if (cpufeat) {
+ cmdline = g_strdup_printf("-cpu %s,%s", cpu, cpufeat);
+ } else {
+ cmdline = g_strdup_printf("-cpu %s", cpu);
+ }
+
args->cmdline = cmdline;
args->in_eax = eax;
args->in_ecx = ecx;
@@ -162,13 +193,17 @@
args->bitnr = bitnr;
args->expected_value = expected_value;
qtest_add_data_func(name, args, test_feature_flag);
- return args;
+ return;
}
static void test_plus_minus_subprocess(void)
{
char *path;
+ if (!qtest_has_cpu_model("pentium")) {
+ return;
+ }
+
/* Rules:
* 1)"-foo" overrides "+foo"
* 2) "[+-]foo" overrides "foo=..."
@@ -198,6 +233,10 @@
static void test_plus_minus(void)
{
+ if (!qtest_has_cpu_model("pentium")) {
+ return;
+ }
+
g_test_trap_subprocess("/x86/cpuid/parsing-plus-minus/subprocess", 0, 0);
g_test_trap_assert_passed();
g_test_trap_assert_stderr("*Ambiguous CPU model string. "
@@ -217,99 +256,105 @@
/* Original level values for CPU models: */
add_cpuid_test("x86/cpuid/phenom/level",
- "-cpu phenom", "level", 5);
+ "phenom", NULL, NULL, "level", 5);
add_cpuid_test("x86/cpuid/Conroe/level",
- "-cpu Conroe", "level", 10);
+ "Conroe", NULL, NULL, "level", 10);
add_cpuid_test("x86/cpuid/SandyBridge/level",
- "-cpu SandyBridge", "level", 0xd);
+ "SandyBridge", NULL, NULL, "level", 0xd);
add_cpuid_test("x86/cpuid/486/xlevel",
- "-cpu 486", "xlevel", 0);
+ "486", NULL, NULL, "xlevel", 0);
add_cpuid_test("x86/cpuid/core2duo/xlevel",
- "-cpu core2duo", "xlevel", 0x80000008);
+ "core2duo", NULL, NULL, "xlevel", 0x80000008);
add_cpuid_test("x86/cpuid/phenom/xlevel",
- "-cpu phenom", "xlevel", 0x8000001A);
+ "phenom", NULL, NULL, "xlevel", 0x8000001A);
add_cpuid_test("x86/cpuid/athlon/xlevel",
- "-cpu athlon", "xlevel", 0x80000008);
+ "athlon", NULL, NULL, "xlevel", 0x80000008);
/* If level is not large enough, it should increase automatically: */
/* CPUID[6].EAX: */
- add_cpuid_test("x86/cpuid/auto-level/phenom/arat",
- "-cpu 486,arat=on", "level", 6);
+ add_cpuid_test("x86/cpuid/auto-level/486/arat",
+ "486", "arat=on", NULL, "level", 6);
/* CPUID[EAX=7,ECX=0].EBX: */
add_cpuid_test("x86/cpuid/auto-level/phenom/fsgsbase",
- "-cpu phenom,fsgsbase=on", "level", 7);
+ "phenom", "fsgsbase=on", NULL, "level", 7);
/* CPUID[EAX=7,ECX=0].ECX: */
add_cpuid_test("x86/cpuid/auto-level/phenom/avx512vbmi",
- "-cpu phenom,avx512vbmi=on", "level", 7);
+ "phenom", "avx512vbmi=on", NULL, "level", 7);
/* CPUID[EAX=0xd,ECX=1].EAX: */
add_cpuid_test("x86/cpuid/auto-level/phenom/xsaveopt",
- "-cpu phenom,xsaveopt=on", "level", 0xd);
+ "phenom", "xsaveopt=on", NULL, "level", 0xd);
/* CPUID[8000_0001].EDX: */
add_cpuid_test("x86/cpuid/auto-xlevel/486/3dnow",
- "-cpu 486,3dnow=on", "xlevel", 0x80000001);
+ "486", "3dnow=on", NULL, "xlevel", 0x80000001);
/* CPUID[8000_0001].ECX: */
add_cpuid_test("x86/cpuid/auto-xlevel/486/sse4a",
- "-cpu 486,sse4a=on", "xlevel", 0x80000001);
+ "486", "sse4a=on", NULL, "xlevel", 0x80000001);
/* CPUID[8000_0007].EDX: */
add_cpuid_test("x86/cpuid/auto-xlevel/486/invtsc",
- "-cpu 486,invtsc=on", "xlevel", 0x80000007);
+ "486", "invtsc=on", NULL, "xlevel", 0x80000007);
/* CPUID[8000_000A].EDX: */
add_cpuid_test("x86/cpuid/auto-xlevel/486/npt",
- "-cpu 486,svm=on,npt=on", "xlevel", 0x8000000A);
+ "486", "svm=on,npt=on", NULL, "xlevel", 0x8000000A);
/* CPUID[C000_0001].EDX: */
add_cpuid_test("x86/cpuid/auto-xlevel2/phenom/xstore",
- "-cpu phenom,xstore=on", "xlevel2", 0xC0000001);
+ "phenom", "xstore=on", NULL, "xlevel2", 0xC0000001);
/* SVM needs CPUID[0x8000000A] */
add_cpuid_test("x86/cpuid/auto-xlevel/athlon/svm",
- "-cpu athlon,svm=on", "xlevel", 0x8000000A);
+ "athlon", "svm=on", NULL, "xlevel", 0x8000000A);
/* If level is already large enough, it shouldn't change: */
add_cpuid_test("x86/cpuid/auto-level/SandyBridge/multiple",
- "-cpu SandyBridge,arat=on,fsgsbase=on,avx512vbmi=on",
- "level", 0xd);
+ "SandyBridge", "arat=on,fsgsbase=on,avx512vbmi=on",
+ NULL, "level", 0xd);
/* If level is explicitly set, it shouldn't change: */
add_cpuid_test("x86/cpuid/auto-level/486/fixed/0xF",
- "-cpu 486,level=0xF,arat=on,fsgsbase=on,avx512vbmi=on,xsaveopt=on",
- "level", 0xF);
+ "486",
+ "level=0xF,arat=on,fsgsbase=on,avx512vbmi=on,xsaveopt=on",
+ NULL, "level", 0xF);
add_cpuid_test("x86/cpuid/auto-level/486/fixed/2",
- "-cpu 486,level=2,arat=on,fsgsbase=on,avx512vbmi=on,xsaveopt=on",
- "level", 2);
+ "486",
+ "level=2,arat=on,fsgsbase=on,avx512vbmi=on,xsaveopt=on",
+ NULL, "level", 2);
add_cpuid_test("x86/cpuid/auto-level/486/fixed/0",
- "-cpu 486,level=0,arat=on,fsgsbase=on,avx512vbmi=on,xsaveopt=on",
- "level", 0);
+ "486",
+ "level=0,arat=on,fsgsbase=on,avx512vbmi=on,xsaveopt=on",
+ NULL, "level", 0);
/* if xlevel is already large enough, it shouldn't change: */
add_cpuid_test("x86/cpuid/auto-xlevel/phenom/3dnow",
- "-cpu phenom,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
- "xlevel", 0x8000001A);
+ "phenom", "3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
+ NULL, "xlevel", 0x8000001A);
/* If xlevel is explicitly set, it shouldn't change: */
add_cpuid_test("x86/cpuid/auto-xlevel/486/fixed/80000002",
- "-cpu 486,xlevel=0x80000002,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
- "xlevel", 0x80000002);
+ "486",
+ "xlevel=0x80000002,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
+ NULL, "xlevel", 0x80000002);
add_cpuid_test("x86/cpuid/auto-xlevel/486/fixed/8000001A",
- "-cpu 486,xlevel=0x8000001A,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
- "xlevel", 0x8000001A);
+ "486",
+ "xlevel=0x8000001A,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
+ NULL, "xlevel", 0x8000001A);
add_cpuid_test("x86/cpuid/auto-xlevel/phenom/fixed/0",
- "-cpu 486,xlevel=0,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
- "xlevel", 0);
+ "486",
+ "xlevel=0,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
+ NULL, "xlevel", 0);
/* if xlevel2 is already large enough, it shouldn't change: */
add_cpuid_test("x86/cpuid/auto-xlevel2/486/fixed",
- "-cpu 486,xlevel2=0xC0000002,xstore=on",
- "xlevel2", 0xC0000002);
+ "486", "xlevel2=0xC0000002,xstore=on",
+ NULL, "xlevel2", 0xC0000002);
/* Check compatibility of old machine-types that didn't
* auto-increase level/xlevel/xlevel2: */
if (qtest_has_machine("pc-i440fx-2.7")) {
add_cpuid_test("x86/cpuid/auto-level/pc-2.7",
- "-machine pc-i440fx-2.7 -cpu 486,arat=on,avx512vbmi=on,xsaveopt=on",
- "level", 1);
+ "486", "arat=on,avx512vbmi=on,xsaveopt=on",
+ "pc-i440fx-2.7", "level", 1);
add_cpuid_test("x86/cpuid/auto-xlevel/pc-2.7",
- "-machine pc-i440fx-2.7 -cpu 486,3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
- "xlevel", 0);
+ "486", "3dnow=on,sse4a=on,invtsc=on,npt=on,svm=on",
+ "pc-i440fx-2.7", "xlevel", 0);
add_cpuid_test("x86/cpuid/auto-xlevel2/pc-2.7",
- "-machine pc-i440fx-2.7 -cpu 486,xstore=on",
+ "486", "xstore=on", "pc-i440fx-2.7",
"xlevel2", 0);
}
/*
@@ -319,18 +364,18 @@
*/
if (qtest_has_machine("pc-i440fx-2.3")) {
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.3/off",
- "-machine pc-i440fx-2.3 -cpu Penryn",
+ "Penryn", NULL, "pc-i440fx-2.3",
"level", 4);
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.3/on",
- "-machine pc-i440fx-2.3 -cpu Penryn,erms=on",
+ "Penryn", "erms=on", "pc-i440fx-2.3",
"level", 7);
}
if (qtest_has_machine("pc-i440fx-2.9")) {
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.9/off",
- "-machine pc-i440fx-2.9 -cpu Conroe",
+ "Conroe", NULL, "pc-i440fx-2.9",
"level", 10);
add_cpuid_test("x86/cpuid/auto-level7/pc-i440fx-2.9/on",
- "-machine pc-i440fx-2.9 -cpu Conroe,erms=on",
+ "Conroe", "erms=on", "pc-i440fx-2.9",
"level", 10);
}
@@ -341,42 +386,43 @@
*/
if (qtest_has_machine("pc-i440fx-2.3")) {
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.3",
- "-machine pc-i440fx-2.3 -cpu SandyBridge",
+ "SandyBridge", NULL, "pc-i440fx-2.3",
"xlevel", 0x8000000a);
}
if (qtest_has_machine("pc-i440fx-2.4")) {
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-off",
- "-machine pc-i440fx-2.4 -cpu SandyBridge,",
+ "SandyBridge", NULL, "pc-i440fx-2.4",
"xlevel", 0x80000008);
add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-on",
- "-machine pc-i440fx-2.4 -cpu SandyBridge,svm=on,npt=on",
+ "SandyBridge", "svm=on,npt=on", "pc-i440fx-2.4",
"xlevel", 0x80000008);
}
/* Test feature parsing */
add_feature_test("x86/cpuid/features/plus",
- "-cpu 486,+arat",
+ "486", "+arat",
6, 0, "EAX", 2, true);
add_feature_test("x86/cpuid/features/minus",
- "-cpu pentium,-mmx",
+ "pentium", "-mmx",
1, 0, "EDX", 23, false);
add_feature_test("x86/cpuid/features/on",
- "-cpu 486,arat=on",
+ "486", "arat=on",
6, 0, "EAX", 2, true);
add_feature_test("x86/cpuid/features/off",
- "-cpu pentium,mmx=off",
+ "pentium", "mmx=off",
1, 0, "EDX", 23, false);
+
add_feature_test("x86/cpuid/features/max-plus-invtsc",
- "-cpu max,+invtsc",
+ "max" , "+invtsc",
0x80000007, 0, "EDX", 8, true);
add_feature_test("x86/cpuid/features/max-invtsc-on",
- "-cpu max,invtsc=on",
+ "max", "invtsc=on",
0x80000007, 0, "EDX", 8, true);
add_feature_test("x86/cpuid/features/max-minus-mmx",
- "-cpu max,-mmx",
+ "max", "-mmx",
1, 0, "EDX", 23, false);
add_feature_test("x86/cpuid/features/max-invtsc-on,mmx=off",
- "-cpu max,mmx=off",
+ "max", "mmx=off",
1, 0, "EDX", 23, false);
return g_test_run();
diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target
index 80159cc..4c8e15e 100644
--- a/tests/tcg/s390x/Makefile.softmmu-target
+++ b/tests/tcg/s390x/Makefile.softmmu-target
@@ -1,6 +1,6 @@
S390X_SRC=$(SRC_PATH)/tests/tcg/s390x
VPATH+=$(S390X_SRC)
-QEMU_OPTS=-action panic=exit-failure -nographic -kernel
+QEMU_OPTS+=-action panic=exit-failure -nographic $(EXTFLAGS) -kernel
LINK_SCRIPT=$(S390X_SRC)/softmmu.ld
CFLAGS+=-ggdb -O0
LDFLAGS=-nostdlib -static
diff --git a/tests/unit/test-crypto-block.c b/tests/unit/test-crypto-block.c
index 6cfc817..42cfab6 100644
--- a/tests/unit/test-crypto-block.c
+++ b/tests/unit/test-crypto-block.c
@@ -303,7 +303,6 @@
test_block_read_func,
&header,
0,
- 1,
NULL);
g_assert(blk == NULL);
@@ -312,7 +311,6 @@
test_block_read_func,
&header,
QCRYPTO_BLOCK_OPEN_NO_IO,
- 1,
&error_abort);
g_assert(qcrypto_block_get_cipher(blk) == NULL);
@@ -327,7 +325,6 @@
test_block_read_func,
&header,
0,
- 1,
&error_abort);
g_assert(blk);
@@ -384,7 +381,6 @@
test_block_read_func,
&buf,
0,
- 1,
&err);
g_assert(!blk);
g_assert(err);
diff --git a/tests/unit/test-smp-parse.c b/tests/unit/test-smp-parse.c
index 9fdba24..f9bccb5 100644
--- a/tests/unit/test-smp-parse.c
+++ b/tests/unit/test-smp-parse.c
@@ -48,17 +48,19 @@
}
/*
- * Currently a 4-level topology hierarchy is supported on PC machines
- * -sockets/dies/cores/threads
+ * Currently a 5-level topology hierarchy is supported on PC machines
+ * -sockets/dies/modules/cores/threads
*/
-#define SMP_CONFIG_WITH_DIES(ha, a, hb, b, hc, c, hd, d, he, e, hf, f) \
+#define SMP_CONFIG_WITH_MODS_DIES(ha, a, hb, b, hc, c, hd, d, \
+ he, e, hf, f, hg, g) \
{ \
.has_cpus = ha, .cpus = a, \
.has_sockets = hb, .sockets = b, \
.has_dies = hc, .dies = c, \
- .has_cores = hd, .cores = d, \
- .has_threads = he, .threads = e, \
- .has_maxcpus = hf, .maxcpus = f, \
+ .has_modules = hd, .modules = d, \
+ .has_cores = he, .cores = e, \
+ .has_threads = hf, .threads = f, \
+ .has_maxcpus = hg, .maxcpus = g, \
}
/*
@@ -92,11 +94,11 @@
}
/*
- * Currently QEMU supports up to a 7-level topology hierarchy, which is the
+ * Currently QEMU supports up to a 8-level topology hierarchy, which is the
* QEMU's unified abstract representation of CPU topology.
- * -drawers/books/sockets/dies/clusters/cores/threads
+ * -drawers/books/sockets/dies/clusters/modules/cores/threads
*/
-#define SMP_CONFIG_WITH_FULL_TOPO(a, b, c, d, e, f, g, h, i) \
+#define SMP_CONFIG_WITH_FULL_TOPO(a, b, c, d, e, f, g, h, i, j) \
{ \
.has_cpus = true, .cpus = a, \
.has_drawers = true, .drawers = b, \
@@ -104,9 +106,10 @@
.has_sockets = true, .sockets = d, \
.has_dies = true, .dies = e, \
.has_clusters = true, .clusters = f, \
- .has_cores = true, .cores = g, \
- .has_threads = true, .threads = h, \
- .has_maxcpus = true, .maxcpus = i, \
+ .has_modules = true, .modules = g, \
+ .has_cores = true, .cores = h, \
+ .has_threads = true, .threads = i, \
+ .has_maxcpus = true, .maxcpus = j, \
}
/**
@@ -333,9 +336,11 @@
}, {
/*
* Unsupported parameters are always allowed to be set to '1'
- * config: -smp 8,books=1,drawers=1,sockets=2,modules=1,dies=1,cores=2,threads=2,maxcpus=8
+ * config:
+ * -smp 8,drawers=1,books=1,sockets=2,dies=1,clusters=1,modules=1,\
+ * cores=2,threads=2,maxcpus=8
* expect: cpus=8,sockets=2,cores=2,threads=2,maxcpus=8 */
- .config = SMP_CONFIG_WITH_FULL_TOPO(8, 1, 1, 2, 1, 1, 2, 2, 8),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(8, 1, 1, 2, 1, 1, 1, 2, 2, 8),
.expect_prefer_sockets = CPU_TOPOLOGY_GENERIC(8, 2, 2, 2, 8),
.expect_prefer_cores = CPU_TOPOLOGY_GENERIC(8, 2, 2, 2, 8),
},
@@ -343,8 +348,14 @@
static const struct SMPTestData data_generic_invalid[] = {
{
+ /* config: -smp 2,modules=2 */
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 2, F, 0, F, 0, T, 2,
+ F, 0, F, 0, F, 0),
+ .expect_error = "modules > 1 not supported by this machine's CPU topology",
+ }, {
/* config: -smp 2,dies=2 */
- .config = SMP_CONFIG_WITH_DIES(T, 2, F, 0, T, 2, F, 0, F, 0, F, 0),
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 2, F, 0, T, 2, F, 0,
+ F, 0, F, 0, F, 0),
.expect_error = "dies > 1 not supported by this machine's CPU topology",
}, {
/* config: -smp 2,clusters=2 */
@@ -395,17 +406,39 @@
},
};
+static const struct SMPTestData data_with_modules_invalid[] = {
+ {
+ /* config: -smp 16,sockets=2,modules=2,cores=4,threads=2,maxcpus=16 */
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 16, T, 2, F, 0, T, 2,
+ T, 4, T, 2, T, 16),
+ .expect_error = "Invalid CPU topology: "
+ "product of the hierarchy must match maxcpus: "
+ "sockets (2) * modules (2) * cores (4) * threads (2) "
+ "!= maxcpus (16)",
+ }, {
+ /* config: -smp 34,sockets=2,modules=2,cores=4,threads=2,maxcpus=32 */
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 34, T, 2, F, 0, T, 2,
+ T, 4, T, 2, T, 32),
+ .expect_error = "Invalid CPU topology: "
+ "maxcpus must be equal to or greater than smp: "
+ "sockets (2) * modules (2) * cores (4) * threads (2) "
+ "== maxcpus (32) < smp_cpus (34)",
+ },
+};
+
static const struct SMPTestData data_with_dies_invalid[] = {
{
/* config: -smp 16,sockets=2,dies=2,cores=4,threads=2,maxcpus=16 */
- .config = SMP_CONFIG_WITH_DIES(T, 16, T, 2, T, 2, T, 4, T, 2, T, 16),
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 16, T, 2, T, 2, F, 0,
+ T, 4, T, 2, T, 16),
.expect_error = "Invalid CPU topology: "
"product of the hierarchy must match maxcpus: "
"sockets (2) * dies (2) * cores (4) * threads (2) "
"!= maxcpus (16)",
}, {
/* config: -smp 34,sockets=2,dies=2,cores=4,threads=2,maxcpus=32 */
- .config = SMP_CONFIG_WITH_DIES(T, 34, T, 2, T, 2, T, 4, T, 2, T, 32),
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 34, T, 2, T, 2, F, 0,
+ T, 4, T, 2, T, 32),
.expect_error = "Invalid CPU topology: "
"maxcpus must be equal to or greater than smp: "
"sockets (2) * dies (2) * cores (4) * threads (2) "
@@ -413,6 +446,33 @@
},
};
+static const struct SMPTestData data_with_modules_dies_invalid[] = {
+ {
+ /*
+ * config: -smp 200,sockets=3,dies=5,modules=2,cores=4,\
+ * threads=2,maxcpus=200
+ */
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 200, T, 3, T, 5, T,
+ 2, T, 4, T, 2, T, 200),
+ .expect_error = "Invalid CPU topology: "
+ "product of the hierarchy must match maxcpus: "
+ "sockets (3) * dies (5) * modules (2) * "
+ "cores (4) * threads (2) != maxcpus (200)",
+ }, {
+ /*
+ * config: -smp 242,sockets=3,dies=5,modules=2,cores=4,\
+ * threads=2,maxcpus=240
+ */
+ .config = SMP_CONFIG_WITH_MODS_DIES(T, 242, T, 3, T, 5, T,
+ 2, T, 4, T, 2, T, 240),
+ .expect_error = "Invalid CPU topology: "
+ "maxcpus must be equal to or greater than smp: "
+ "sockets (3) * dies (5) * modules (2) * "
+ "cores (4) * threads (2) "
+ "== maxcpus (240) < smp_cpus (242)",
+ },
+};
+
static const struct SMPTestData data_with_clusters_invalid[] = {
{
/* config: -smp 16,sockets=2,clusters=2,cores=4,threads=2,maxcpus=16 */
@@ -434,7 +494,7 @@
static const struct SMPTestData data_with_books_invalid[] = {
{
/* config: -smp 16,books=2,sockets=2,cores=4,threads=2,maxcpus=16 */
- .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 16, F, 1, T, 2, T,
+ .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 16, F, 0, T, 2, T,
2, T, 4, T, 2, T, 16),
.expect_error = "Invalid CPU topology: "
"product of the hierarchy must match maxcpus: "
@@ -442,7 +502,7 @@
"!= maxcpus (16)",
}, {
/* config: -smp 34,books=2,sockets=2,cores=4,threads=2,maxcpus=32 */
- .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 34, F, 1, T, 2, T,
+ .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 34, F, 0, T, 2, T,
2, T, 4, T, 2, T, 32),
.expect_error = "Invalid CPU topology: "
"maxcpus must be equal to or greater than smp: "
@@ -454,7 +514,7 @@
static const struct SMPTestData data_with_drawers_invalid[] = {
{
/* config: -smp 16,drawers=2,sockets=2,cores=4,threads=2,maxcpus=16 */
- .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 16, T, 2, F, 1, T,
+ .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 16, T, 2, F, 0, T,
2, T, 4, T, 2, T, 16),
.expect_error = "Invalid CPU topology: "
"product of the hierarchy must match maxcpus: "
@@ -462,7 +522,7 @@
"!= maxcpus (16)",
}, {
/* config: -smp 34,drawers=2,sockets=2,cores=4,threads=2,maxcpus=32 */
- .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 34, T, 2, F, 1, T,
+ .config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 34, T, 2, F, 0, T,
2, T, 4, T, 2, T, 32),
.expect_error = "Invalid CPU topology: "
"maxcpus must be equal to or greater than smp: "
@@ -474,8 +534,8 @@
static const struct SMPTestData data_with_drawers_books_invalid[] = {
{
/*
- * config: -smp 200,drawers=2,books=2,sockets=2,cores=4,\
- * threads=2,maxcpus=200
+ * config: -smp 200,drawers=3,books=5,sockets=2,cores=4,\
+ * threads=2,maxcpus=200
*/
.config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 200, T, 3, T, 5, T,
2, T, 4, T, 2, T, 200),
@@ -485,8 +545,8 @@
"cores (4) * threads (2) != maxcpus (200)",
}, {
/*
- * config: -smp 242,drawers=2,books=2,sockets=2,cores=4,\
- * threads=2,maxcpus=240
+ * config: -smp 242,drawers=3,books=5,sockets=2,cores=4,\
+ * threads=2,maxcpus=240
*/
.config = SMP_CONFIG_WITH_BOOKS_DRAWERS(T, 242, T, 3, T, 5, T,
2, T, 4, T, 2, T, 240),
@@ -502,32 +562,37 @@
{
/*
* config: -smp 200,drawers=3,books=5,sockets=2,dies=4,\
- * clusters=2,cores=7,threads=2,maxcpus=200
+ * clusters=2,modules=3,cores=7,threads=2,\
+ * maxcpus=200
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(200, 3, 5, 2, 4, 2, 7, 2, 200),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(200, 3, 5, 2, 4, 2, 3, 7, 2, 200),
.expect_error = "Invalid CPU topology: "
"product of the hierarchy must match maxcpus: "
"drawers (3) * books (5) * sockets (2) * dies (4) * "
- "clusters (2) * cores (7) * threads (2) "
+ "clusters (2) * modules (3) * cores (7) * threads (2) "
"!= maxcpus (200)",
}, {
/*
- * config: -smp 3361,drawers=3,books=5,sockets=2,dies=4,\
- * clusters=2,cores=7,threads=2,maxcpus=3360
+ * config: -smp 2881,drawers=3,books=5,sockets=2,dies=4,\
+ * clusters=2,modules=3,cores=2,threads=2,
+ * maxcpus=2880
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(3361, 3, 5, 2, 4, 2, 7, 2, 3360),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(2881, 3, 5, 2, 4,
+ 2, 3, 2, 2, 2880),
.expect_error = "Invalid CPU topology: "
"maxcpus must be equal to or greater than smp: "
- "drawers (3) * books (5) * sockets (2) * dies (4) * "
- "clusters (2) * cores (7) * threads (2) "
- "== maxcpus (3360) < smp_cpus (3361)",
+ "drawers (3) * books (5) * sockets (2) * "
+ "dies (4) * clusters (2) * modules (3) * "
+ "cores (2) * threads (2) == maxcpus (2880) "
+ "< smp_cpus (2881)",
}, {
/*
* config: -smp 1,drawers=3,books=5,sockets=2,dies=4,\
- * clusters=2,cores=7,threads=3,maxcpus=5040
+ * clusters=2,modules=3,cores=3,threads=3,\
+ * maxcpus=6480
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(3361, 3, 5, 2, 4, 2, 7, 3, 5040),
- .expect_error = "Invalid SMP CPUs 5040. The max CPUs supported "
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 3, 5, 2, 4, 2, 3, 3, 3, 6480),
+ .expect_error = "Invalid SMP CPUs 6480. The max CPUs supported "
"by machine '" SMP_MACHINE_NAME "' is 4096",
},
};
@@ -537,81 +602,100 @@
/*
* Test "cpus=0".
* config: -smp 0,drawers=1,books=1,sockets=1,dies=1,\
- * clusters=1,cores=1,threads=1,maxcpus=1
+ * clusters=1,modules=1,cores=1,threads=1,\
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(0, 1, 1, 1, 1, 1, 1, 1, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(0, 1, 1, 1, 1, 1, 1, 1, 1, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "drawers=0".
* config: -smp 1,drawers=0,books=1,sockets=1,dies=1,\
- * clusters=1,cores=1,threads=1,maxcpus=1
+ * clusters=1,modules=1,cores=1,threads=1,\
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 0, 1, 1, 1, 1, 1, 1, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 0, 1, 1, 1, 1, 1, 1, 1, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "books=0".
* config: -smp 1,drawers=1,books=0,sockets=1,dies=1,\
- * clusters=1,cores=1,threads=1,maxcpus=1
+ * clusters=1,modules=1,cores=1,threads=1,\
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 0, 1, 1, 1, 1, 1, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 0, 1, 1, 1, 1, 1, 1, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "sockets=0".
* config: -smp 1,drawers=1,books=1,sockets=0,dies=1,\
- * clusters=1,cores=1,threads=1,maxcpus=1
+ * clusters=1,modules=1,cores=1,threads=1,
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 0, 1, 1, 1, 1, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 0, 1, 1, 1, 1, 1, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "dies=0".
* config: -smp 1,drawers=1,books=1,sockets=1,dies=0,\
- * clusters=1,cores=1,threads=1,maxcpus=1
+ * clusters=1,modules=1,cores=1,threads=1,\
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 0, 1, 1, 1, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 0, 1, 1, 1, 1, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "clusters=0".
* config: -smp 1,drawers=1,books=1,sockets=1,dies=1,\
- * clusters=0,cores=1,threads=1,maxcpus=1
+ * clusters=0,modules=1,cores=1,threads=1,\
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 0, 1, 1, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 0, 1, 1, 1, 1),
+ .expect_error = "Invalid CPU topology: CPU topology parameters must "
+ "be greater than zero",
+ }, {
+ /*
+ * Test "modules=0".
+ * config: -smp 1,drawers=1,books=1,sockets=1,dies=1,\
+ * clusters=1,modules=0,cores=1,threads=1,\
+ * maxcpus=1
+ */
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 1, 0, 1, 1, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "cores=0".
* config: -smp 1,drawers=1,books=1,sockets=1,dies=1,\
- * clusters=1,cores=0,threads=1,maxcpus=1
+ * clusters=1,modules=1,cores=0,threads=1,
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 1, 0, 1, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 1, 1, 0, 1, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "threads=0".
* config: -smp 1,drawers=1,books=1,sockets=1,dies=1,\
- * clusters=1,cores=1,threads=0,maxcpus=1
+ * clusters=1,modules=1,cores=1,threads=0,\
+ * maxcpus=1
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 1, 1, 0, 1),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 1, 1, 1, 0, 1),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
}, {
/*
* Test "maxcpus=0".
* config: -smp 1,drawers=1,books=1,sockets=1,dies=1,\
- * clusters=1,cores=1,threads=1,maxcpus=0
+ * clusters=1,modules=1,cores=1,threads=1,\
+ * maxcpus=0
*/
- .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 1, 1, 1, 0),
+ .config = SMP_CONFIG_WITH_FULL_TOPO(1, 1, 1, 1, 1, 1, 1, 1, 1, 0),
.expect_error = "Invalid CPU topology: CPU topology parameters must "
"be greater than zero",
},
@@ -627,6 +711,7 @@
" .has_sockets = %5s, sockets = %" PRId64 ",\n"
" .has_dies = %5s, dies = %" PRId64 ",\n"
" .has_clusters = %5s, clusters = %" PRId64 ",\n"
+ " .has_modules = %5s, modules = %" PRId64 ",\n"
" .has_cores = %5s, cores = %" PRId64 ",\n"
" .has_threads = %5s, threads = %" PRId64 ",\n"
" .has_maxcpus = %5s, maxcpus = %" PRId64 ",\n"
@@ -637,6 +722,7 @@
config->has_sockets ? "true" : "false", config->sockets,
config->has_dies ? "true" : "false", config->dies,
config->has_clusters ? "true" : "false", config->clusters,
+ config->has_modules ? "true" : "false", config->modules,
config->has_cores ? "true" : "false", config->cores,
config->has_threads ? "true" : "false", config->threads,
config->has_maxcpus ? "true" : "false", config->maxcpus);
@@ -677,6 +763,7 @@
" .sockets = %u,\n"
" .dies = %u,\n"
" .clusters = %u,\n"
+ " .modules = %u,\n"
" .cores = %u,\n"
" .threads = %u,\n"
" .max_cpus = %u,\n"
@@ -686,8 +773,8 @@
"}",
topo->cpus, topo->drawers, topo->books,
topo->sockets, topo->dies, topo->clusters,
- topo->cores, topo->threads, topo->max_cpus,
- threads_per_socket, cores_per_socket,
+ topo->modules, topo->cores, topo->threads,
+ topo->max_cpus, threads_per_socket, cores_per_socket,
has_clusters ? "true" : "false");
}
@@ -730,6 +817,7 @@
(ms->smp.sockets == expect_topo->sockets) &&
(ms->smp.dies == expect_topo->dies) &&
(ms->smp.clusters == expect_topo->clusters) &&
+ (ms->smp.modules == expect_topo->modules) &&
(ms->smp.cores == expect_topo->cores) &&
(ms->smp.threads == expect_topo->threads) &&
(ms->smp.max_cpus == expect_topo->max_cpus) &&
@@ -810,6 +898,11 @@
/* The parsed results of the unsupported parameters should be 1 */
static void unsupported_params_init(const MachineClass *mc, SMPTestData *data)
{
+ if (!mc->smp_props.modules_supported) {
+ data->expect_prefer_sockets.modules = 1;
+ data->expect_prefer_cores.modules = 1;
+ }
+
if (!mc->smp_props.dies_supported) {
data->expect_prefer_sockets.dies = 1;
data->expect_prefer_cores.dies = 1;
@@ -850,6 +943,13 @@
mc->max_cpus = MAX_CPUS - 1;
}
+static void machine_with_modules_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->smp_props.modules_supported = true;
+}
+
static void machine_with_dies_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -857,6 +957,14 @@
mc->smp_props.dies_supported = true;
}
+static void machine_with_modules_dies_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->smp_props.modules_supported = true;
+ mc->smp_props.dies_supported = true;
+}
+
static void machine_with_clusters_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -894,6 +1002,7 @@
mc->smp_props.books_supported = true;
mc->smp_props.dies_supported = true;
mc->smp_props.clusters_supported = true;
+ mc->smp_props.modules_supported = true;
}
static void test_generic_valid(const void *opaque)
@@ -934,6 +1043,56 @@
object_unref(obj);
}
+static void test_with_modules(const void *opaque)
+{
+ const char *machine_type = opaque;
+ Object *obj = object_new(machine_type);
+ MachineState *ms = MACHINE(obj);
+ MachineClass *mc = MACHINE_GET_CLASS(obj);
+ SMPTestData data = {};
+ unsigned int num_modules = 2;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(data_generic_valid); i++) {
+ data = data_generic_valid[i];
+ unsupported_params_init(mc, &data);
+
+ /* when modules parameter is omitted, it will be set as 1 */
+ data.expect_prefer_sockets.modules = 1;
+ data.expect_prefer_cores.modules = 1;
+
+ smp_parse_test(ms, &data, true);
+
+ /* when modules parameter is specified */
+ data.config.has_modules = true;
+ data.config.modules = num_modules;
+ if (data.config.has_cpus) {
+ data.config.cpus *= num_modules;
+ }
+ if (data.config.has_maxcpus) {
+ data.config.maxcpus *= num_modules;
+ }
+
+ data.expect_prefer_sockets.modules = num_modules;
+ data.expect_prefer_sockets.cpus *= num_modules;
+ data.expect_prefer_sockets.max_cpus *= num_modules;
+ data.expect_prefer_cores.modules = num_modules;
+ data.expect_prefer_cores.cpus *= num_modules;
+ data.expect_prefer_cores.max_cpus *= num_modules;
+
+ smp_parse_test(ms, &data, true);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(data_with_modules_invalid); i++) {
+ data = data_with_modules_invalid[i];
+ unsupported_params_init(mc, &data);
+
+ smp_parse_test(ms, &data, false);
+ }
+
+ object_unref(obj);
+}
+
static void test_with_dies(const void *opaque)
{
const char *machine_type = opaque;
@@ -984,6 +1143,67 @@
object_unref(obj);
}
+static void test_with_modules_dies(const void *opaque)
+{
+ const char *machine_type = opaque;
+ Object *obj = object_new(machine_type);
+ MachineState *ms = MACHINE(obj);
+ MachineClass *mc = MACHINE_GET_CLASS(obj);
+ SMPTestData data = {};
+ unsigned int num_modules = 5, num_dies = 3;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(data_generic_valid); i++) {
+ data = data_generic_valid[i];
+ unsupported_params_init(mc, &data);
+
+ /*
+ * when modules and dies parameters are omitted, they will
+ * be both set as 1.
+ */
+ data.expect_prefer_sockets.modules = 1;
+ data.expect_prefer_sockets.dies = 1;
+ data.expect_prefer_cores.modules = 1;
+ data.expect_prefer_cores.dies = 1;
+
+ smp_parse_test(ms, &data, true);
+
+ /* when modules and dies parameters are both specified */
+ data.config.has_modules = true;
+ data.config.modules = num_modules;
+ data.config.has_dies = true;
+ data.config.dies = num_dies;
+
+ if (data.config.has_cpus) {
+ data.config.cpus *= num_modules * num_dies;
+ }
+ if (data.config.has_maxcpus) {
+ data.config.maxcpus *= num_modules * num_dies;
+ }
+
+ data.expect_prefer_sockets.modules = num_modules;
+ data.expect_prefer_sockets.dies = num_dies;
+ data.expect_prefer_sockets.cpus *= num_modules * num_dies;
+ data.expect_prefer_sockets.max_cpus *= num_modules * num_dies;
+
+ data.expect_prefer_cores.modules = num_modules;
+ data.expect_prefer_cores.dies = num_dies;
+ data.expect_prefer_cores.cpus *= num_modules * num_dies;
+ data.expect_prefer_cores.max_cpus *= num_modules * num_dies;
+
+ smp_parse_test(ms, &data, true);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(data_with_modules_dies_invalid); i++) {
+ data = data_with_modules_dies_invalid[i];
+ unsupported_params_init(mc, &data);
+
+ smp_parse_test(ms, &data, false);
+ }
+
+ object_unref(obj);
+}
+
static void test_with_clusters(const void *opaque)
{
const char *machine_type = opaque;
@@ -1202,30 +1422,41 @@
MachineState *ms = MACHINE(obj);
MachineClass *mc = MACHINE_GET_CLASS(obj);
SMPTestData data = {};
- unsigned int drawers = 5, books = 3, dies = 2, clusters = 7, multiplier;
+ unsigned int drawers, books, dies, clusters, modules, multiplier;
int i;
- multiplier = drawers * books * dies * clusters;
+ drawers = 5;
+ books = 3;
+ dies = 2;
+ clusters = 3;
+ modules = 2;
+
+ multiplier = drawers * books * dies * clusters * modules;
for (i = 0; i < ARRAY_SIZE(data_generic_valid); i++) {
data = data_generic_valid[i];
unsupported_params_init(mc, &data);
/*
- * when drawers, books, dies and clusters parameters are omitted,
- * they will be set as 1.
+ * when drawers, books, dies, clusters and modules parameters are
+ * omitted, they will be set as 1.
*/
data.expect_prefer_sockets.drawers = 1;
data.expect_prefer_sockets.books = 1;
data.expect_prefer_sockets.dies = 1;
data.expect_prefer_sockets.clusters = 1;
+ data.expect_prefer_sockets.modules = 1;
data.expect_prefer_cores.drawers = 1;
data.expect_prefer_cores.books = 1;
data.expect_prefer_cores.dies = 1;
data.expect_prefer_cores.clusters = 1;
+ data.expect_prefer_cores.modules = 1;
smp_parse_test(ms, &data, true);
- /* when drawers, books, dies and clusters parameters are specified. */
+ /*
+ * when drawers, books, dies, clusters and modules parameters
+ * are specified.
+ */
data.config.has_drawers = true;
data.config.drawers = drawers;
data.config.has_books = true;
@@ -1234,6 +1465,8 @@
data.config.dies = dies;
data.config.has_clusters = true;
data.config.clusters = clusters;
+ data.config.has_modules = true;
+ data.config.modules = modules;
if (data.config.has_cpus) {
data.config.cpus *= multiplier;
@@ -1246,6 +1479,7 @@
data.expect_prefer_sockets.books = books;
data.expect_prefer_sockets.dies = dies;
data.expect_prefer_sockets.clusters = clusters;
+ data.expect_prefer_sockets.modules = modules;
data.expect_prefer_sockets.cpus *= multiplier;
data.expect_prefer_sockets.max_cpus *= multiplier;
@@ -1253,6 +1487,7 @@
data.expect_prefer_cores.books = books;
data.expect_prefer_cores.dies = dies;
data.expect_prefer_cores.clusters = clusters;
+ data.expect_prefer_cores.modules = modules;
data.expect_prefer_cores.cpus *= multiplier;
data.expect_prefer_cores.max_cpus *= multiplier;
@@ -1293,10 +1528,18 @@
.parent = TYPE_MACHINE,
.class_init = machine_generic_invalid_class_init,
}, {
+ .name = MACHINE_TYPE_NAME("smp-with-modules"),
+ .parent = TYPE_MACHINE,
+ .class_init = machine_with_modules_class_init,
+ }, {
.name = MACHINE_TYPE_NAME("smp-with-dies"),
.parent = TYPE_MACHINE,
.class_init = machine_with_dies_class_init,
}, {
+ .name = MACHINE_TYPE_NAME("smp-with-modules-dies"),
+ .parent = TYPE_MACHINE,
+ .class_init = machine_with_modules_dies_class_init,
+ }, {
.name = MACHINE_TYPE_NAME("smp-with-clusters"),
.parent = TYPE_MACHINE,
.class_init = machine_with_clusters_class_init,
@@ -1333,9 +1576,15 @@
g_test_add_data_func("/test-smp-parse/generic/invalid",
MACHINE_TYPE_NAME("smp-generic-invalid"),
test_generic_invalid);
+ g_test_add_data_func("/test-smp-parse/with_modules",
+ MACHINE_TYPE_NAME("smp-with-modules"),
+ test_with_modules);
g_test_add_data_func("/test-smp-parse/with_dies",
MACHINE_TYPE_NAME("smp-with-dies"),
test_with_dies);
+ g_test_add_data_func("/test-smp-parse/with_modules_dies",
+ MACHINE_TYPE_NAME("smp-with-modules-dies"),
+ test_with_modules_dies);
g_test_add_data_func("/test-smp-parse/with_clusters",
MACHINE_TYPE_NAME("smp-with-clusters"),
test_with_clusters);
